library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_updown is
port (
clk : in std_logic; -- clock input
reset : in std_logic; -- reset
en : in std_logic; -- enable
up : in std_logic; -- up = 1 when counter counts in up direction
otherwise dowm direction
Q : out std_logic_vector(15 downto 0) -- output data
);
end counter_updown;
architecture behavioral of counter_updown is
signal temp : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then -- When reset = '1'
temp <= (others => '0');
elsif (en = '1') then -- when CE = '1'
if (up = '1') then
temp <= temp + '1'; -- counting in up direction
else
temp <= temp - '1'; -- counting in down direction
end if;
else
temp <= temp;
end if;
end if;
end process;
Q <= temp;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity counter_updown_tb is
end counter_updown_tb;
architecture behavior of counter_updown_tb is
-- component declaration for the unit under test (uut)
component counter_updown
port(
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
up : in std_logic;
q : out std_logic_vector(15 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal en : std_logic := '0';
signal up : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: counter_updown port map (
clk => clk,
reset => reset,
en => en,
up => up,
Q => Q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1'; en <= '0';
wait for clk_period*10;
reset <= '0';
en <= '1'; up <= '1';
wait for 100 ns;
en <= '0'; up <= '1';
wait for 50 ns;
en <= '1'; up <= '1';
wait for 300 ns;
en <= '0'; up <= '1';
wait for 100 ns;
en <= '1'; up <= '0';
wait for 200 ns;
en <= '0'; up <= '0';
wait for 100 ns;
en <= '1'; up <= '1';
wait for 100 ns;
wait;
end process;
end;
Waveform
Problem 8 (Lab, 20 points) (1) Write a VHDL module implementing a synchronous 16-bit counter. A...
Consider the circuit in Figure 1. It is a 4-bit (QQ2Q3) synchronous counter which uses four T-type flip-flops. The counter increases its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear signal low. You are to implement an 8-bit counter of this type Enable T Q Clock Clear Figure 1. 4-bit synchronous counter (but you need to implement 8-bit counter in this lab) Specific notes:...
Write a behavioral Verilog module for a 4-bit Johnson counter that has 8 states. The counter loads the "0000" state if reset is low. The counter should start and end with this state. Write a testbench to verify the correctness of the 4-bit Johnson counter. The testbenclh should have a clock with a period of 20ns and a reset signal. The testbench should store the 4-bit binary outputs of the counter in a file, which will be used to provide...
Design C-1 (modulo-10 up-counter): Using the behavioral VHDL coding, create an up-counter to count upward. The up counter has the following control inputs En.reset, CLK. The counting outputs are Q0, O1, Q2. and O3 reset clears the outputs of the counter to 0. En enables the counting when En-1. When En-0, the counter stops. The counter sequentially counts all the possible numbers and loops again, from 0 to 9, back to 0 and 9, etc Design C-2: Ten-second Counter with...
Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-flop (FF) include asynchronous reset and preset signals. Refer to Example 4.3 on page 160 for an example of a single FF with both reset and preset signals as well as with an enable signal. For this project, you don't need to use FFs with enables. You don't also need not-q (nq) in this assignment. Use active-high signals for reset and present signals. The example...
please solve the question completely and show the steps ... thumb up will be given (5 points each) [CO: 6] a. If RO and R1 are both 16-bit serial shift registers, each with a single serial input (S_IN) and a single serial output (S_OUT), clock and reset. Design using RO and Rl additional logic, a circuit that would store the output S_OUT of either RO or Rl into a D-FF based on input CH. If CH is 0, S OUT...
Just need the code for the random counter,Thanks Objective: In this lab, we will learn how we can design sequential circuits using behavioral modelling, and implementing the design in FPGA. Problem: Design a random counter with the following counting sequence: Counting Sequence: 04 2 9 168573 Design Description: The counter has one clock (Clock), one reset (Reset), and one move left or right control signal (L/R) as input. The counter also has one 4bit output O and one 2bit output...