Question

The task is to design a two-bit controlled counter which has two counting bits (Q2, Q1), has one control input C1, and also two extra outputs, one indicating overflow, the other underflow.

When C1=0 the counter counts up by 2s; i.e. 0 becomes 2, 1 becomes 3. In this mode the values 2 and 3 go to the overflow state. When the control input C1=1, the counter counts down by 2s, i.e. 3 becomes 1, and 2 becomes 0, and 1 and 0 go to the underflow state. The counter remains in one of these "error" states until the control bit C1 is changed at which point it goes to state 0. The finite state machine shows this operating sequence.

One way to design this circuit is to set up six states. These are the four output count states: 0, 1, 2, 3, and the two "error" states: OV (overflow) and UN (underflow). In order to provide six internal states, we need a minimum of three flipflops. In the following incomplete transition table six flip flop outputs are assigned, two are left as don't cares.

(a) Complete the transition table by showing the Q3, Q2, Q1 outputs of the "next" state.

(b) Construct three KMaps for the D-FF inputs D3, D2, and D1 and determine the minimised expressions for D3, D2, and D1.

(c) Determine the necessary output circuits which provide the required output signals: Overflow Indicator and Underflow Indicator.

C1 D1- D DIDO Q1 (O2 D21 D 3 Overflow Indicator UN OV Underflow Indicator Clock OUT 0101010101010101 3 a0123 000000001111111

Answer 1

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