Question

Digital Logic Design

Need help with homework.

Also need to create Logisim circuit with results.

Thank you!

Your IDs gn project, spring semester Your name 19 Digital Logic Design. Mid-semester desi This is a synchronous counter desig

QaQb QaQb 00 01 10 00 01 1 10 QcQd 01 01 10n 10 QaQb QaQb 00 01 10 00 01 11 10 01 01 10 10 QaQb QaQb 00 01 11 10 00 01 10 01

Jd- Jc= Kb= Ja- Ka= CERTIFICATION: I certify that this represents my own work exclusively. Sign: My NYIT I.D. is Last Name Fi

Your IDs gn project, spring semester Your name 19 Digital Logic Design. Mid-semester desi This is a synchronous counter design. Tables and Karnaugh maps are provided. Do this alone, do not consult with friends except for general structions guidance-I want to see your design. Design, Synchronous counter. (#2 of 3) (repeat). That is QdQcQbQa-0001 (one), 0010 (t Note: Qa is the I.s.b. Design a synchronous counter from 4 JK flip-flops with outputs Od, Qc, Qb and Qa. hereas Od is the m.s.b. (eights). The counter is to repeat a Fibonaccl sequence, thus: 1,2,3,5,8,13 ), 001 l (three), 01 01 (five), 100 0 (eight), 1 101 (thirteen), frepeat to 0001). Until analyzed, all unused states should have flip-flop controls set to "X" (don't care). There are SEE BELOW FOR A DEFINITION OF A FIBBONACCI SEQUENCE. states. sequence" is one in which a term is the sum of the previous two terms. The state transition table has been set up for you to minimize errors. Please use it and the Karnaugh maps provided to A "Flbonaccl complete your design. I strongly suggest you use a pencil. Current state Next State Controls required by the flip-flops 6 10 10 10 12 13 15 Minimize each map individually, and mark your looping!!!!!!!!
QaQb QaQb 00 01 10 00 01 1 10 QcQd 01 01 10n 10 QaQb QaQb 00 01 10 00 01 11 10 01 01 10 10 QaQb QaQb 00 01 11 10 00 01 10 01 01 10 10 Kb- QaQb QaQb 00 01 10 01 10 01 10 Ka - Did you minimize each map individually, and mark your looping???? What are the equations?
Jd- Jc= Kb= Ja- Ka= CERTIFICATION: I certify that this represents my own work exclusively. Sign: My NYIT I.D. is Last Name First Name: BUILD IT STAPLE screenshots to these pages and hand in next week. Pick screenshots which are representative. Send your circuit to our wonderful TGA via email. Include name and ID. No late acceptance. Be on time for class, for once. EENG-130 (etc) mid-semester design project, spring 2015 Page -3- Last revised on Friday, April 19, 2019 at 10:25 PM
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