Question

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EENG 250 Lab 4 M&N Flip Flop Intorduction: There are four types of latches or flip flop designs that are commonly used in designs. However it is always possible to create a custom design. For example take the JK Flip Flop. It can be built using a D Flip Flop. This can be done using state diagram design processes. As shown in the example below. Characteristic Table for JK FF K 2(t+1) 100 Q(t) 0 1 0 1 0 1 1 1 0(t) Table 1 Figure 1 Next State Table Q(t) J K Q(t+1) 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 K-map JK 00 01 11 10 Q - - - - 0 0 0 1 1 1 1 0 0 1 F(D) = JQ' + KQ an Figure 2 Equipment: Logisim Procedure: This lab uses the same processes to design a custom M&N Flip Flop using two D Flip Flops as a base. It will have two inputs M and N and four outputs. The present state of the outputs will have a lagre effect on the next state of the outputs. The characteristic table for the M&N Flip Flop is shown in Table 2.

Answer 1

Here from the given Characteristic table we can see that,

There is 2 number of inputs namely (M and N). Here there are 4 states of the MN flip flop output as (00, 01, 10 and 11).

Now Based on characteristic table we can draw the state diagram as,

procedure for making State diagram:

we firstly label the states that we are using here that is (00, 01, 10, 11). Now seeing the transition ie in first row that is (00 to 01 for input (00)) then we draw transition using an arrow and on the top of that we write input that is(00) in this case. Now taking all the cases and transition we can able to draw state diagram as,

Now from the state diagram we draw transition table for D-flip flop( here we use two namely D1 and D0).

M	N	Q1(t)	Q0(t)	Q1(t+1)	Q0(t+1)	D1	D0
0	0	0	0	0	1	0	1
0	0	0	1	1	1	1	1
0	0	1	0	0	0	0	0
0	0	1	1	1	0	1	0
0	1	0	0	0	1	0	1
0	1	0	1	0	0	0	0
0	1	1	0	1	1	1	1
0	1	1	1	1	0	1	0
1	0	0	0	1	0	1	0
1	0	0	1	1	1	1	1
1	0	1	0	0	0	0	0
1	0	1	1	0	1	0	1
1	1	0	0	1	1	1	1
1	1	0	1	1	0	1	0
1	1	1	0	0	1	0	1
1	1	1	1	0	0	0	0

Now from the above table we draw K-map for D1 and D0 and try to minimize it.

Hence we have input for D-flip flops are,

and

Now building the design we have,

Now after building the circuit we can observe the output from Q1 and Q0 that shows the states with respect to MN with changing the clock signal.

Now we can see from state diagram the behaviour of the circuit.

Answer 2

Here from the given Characteristic table we can see that,

There is 2 number of inputs namely (M and N). Here there are 4 states of the MN flip flop output as (00, 01, 10 and 11).

Now Based on characteristic table we can draw the state diagram as,

procedure for making State diagram:

we firstly label the states that we are using here that is (00, 01, 10, 11). Now seeing the transition ie in first row that is (00 to 01 for input (00)) then we draw transition using an arrow and on the top of that we write input that is(00) in this case. Now taking all the cases and transition we can able to draw state diagram as,

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Now from the state diagram we draw transition table for D-flip flop( here we use two namely D1 and D0).

M	N	Q1(t)	Q0(t)	Q1(t+1)	Q0(t+1)	D1	D0
0	0	0	0	0	1	0	1
0	0	0	1	1	1	1	1
0	0	1	0	0	0	0	0
0	0	1	1	1	0	1	0
0	1	0	0	0	1	0	1
0	1	0	1	0	0	0	0
0	1	1	0	1	1	1	1
0	1	1	1	1	0	1	0
1	0	0	0	1	0	1	0
1	0	0	1	1	1	1	1
1	0	1	0	0	0	0	0
1	0	1	1	0	1	0	1
1	1	0	0	1	1	1	1
1	1	0	1	1	0	1	0
1	1	1	0	0	1	0	1
1	1	1	1	0	0	0	0

Now from the above table we draw K-map for D1 and D0 and try to minimize it.

For DI, For Dz; : 0,20 10 Oo oli 10 oo ol U 001 1] 09 . I oo po 1 1 (17] Di= Moj tiññ ao tñnal Do=noot ñ ñ og + N & A5

Hence we have input for D-flip flops are,

Di= M.Q1 + M.N.Qo + M.N.Q1

and

Do = N.Q0+ M.V.Q+ NQ6

Now building the design we have,

CLK O 00 Deno Deno . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mo- . . . . FM NOE 2 .

Now after building the circuit we can observe the output from Q1 and Q0 that shows the states with respect to MN with changing the clock signal.

Now we can see from state diagram the behaviour of the circuit.