Question

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Biely describe what you ala In the lab, Including technical detail. / complete paragraphs to receive full credit. 3. Questions/Deliverables: a) What is the difference between sequential and concurrent statements? b) What is the difference between dataflow and algorithmic styles? c) Describe the 3 types of data objects in VHDL 4. Program Code Copy your code here. Please provide comments in your code. This will help me ana code and remove any ambiguity. Provide your code as text, not as a screenshot/ima will be deducted if your code is provided as an image. 1. MUX • Behavioral Model Code

Answer 1

concurrent statement:

VHDL is inherited by a concurrent language.

-All VHDL processes are execute concurrently.

-concurrent signal assignment statements are actually one-line processes.

-process are re-executed if any signal in its sensitivity list is changed.

VHDL statements execute sequentially in a processes:

-sequential statements view hardware from a programmer approach.

concurrent process with sequential execution with in a process offers maximum flexibility.

-supports various levels of abstraction.

-support modelling of concurrent and sequential events are observed in real systems.

2.

DATA FLOW STYLE:

1.It describes a system in terms of how data flows through the system.Data dependencies in the description match those in a typical hardware implementation.

2.A data flow description   directly implies a corresponding gate-level implementation.

3.data flow describes consist of one or more concurrent signal assignment statements.

Algorithmic style:

1.it is the most abstract style.The description is abstract in the sense that it does not directly imply a particular gate-level implementation.

2.it consists of one or more process statements.Each process statement is a single concurrent statement that itself contains one or more sequential statements.

3.sequential statements are executed sequentially by a simulator,the same as the execution of sequential statements in a conventional programming language.

3.

Data objects:

data objects hold values of specified types they are:

1.constants

2.signals

3.variables

constants:

hold the values that cannot be changed.

for example:constant noOfStages:integer:=8;

constant must be declared in package ,entities,architecture or process declarative regions.

signals:

signals can be represented wires,and therefore interconnect components.

signal count: bit_vector(3 downto 0);
initial values may be assigned to signals but are rarely meaningful for synthesis

signal count: bit_vector(3 downto 0):="1010";

variables:

variables are only used in process and subprograms (functions and procedures).An example of a variable declaration and initialization is

variable subcarry:std_logic:='0';

Unlike signals variables do not represent wires or memory elements.variables are used for sequential execution,while signals are used for concurrent execution.For synthesis,variables are usually used for computational purposes.