For the realization of the following state table using T-FF, find the input function of B-FF....
• For the realization of the following state table using D-FF, find the input function of A-FF. (Fig. 01) x=1 x=0 x=1 A B AB у 0 0 0 0 x=0 AB 00 11 11 00 0 1 01 10 01 0 1 1 0 1 0 1 1 0 0 10 Fig. 01 DA = f(X,A,B)= 2m (1, 2, 5, 7) LA DA = f(X,A,B)= 2m (0, 1, 4, 7) DB. DA=f(x,A,B)= 2m (1, 3, 4, 6) DA =...
• On the design process of the count-up counter in Excess-3 code using T-FF which of the following answers are incorrect? The minterm numbers for each Flip Flop: C2 А B D 0 0 0 1 1 1 0 1 0 0 2 0 1 0 1 3 0 1 1 0 4 0 1 1 5 1 0 0 0 61 0 1 7 1 0 0 8 1 0 9 1 1 0 0 0 0 0 1...
6. (a) Each clock cycle, an input is provided to the finite state machine (FSM) below. Assuming that we start at state 00 and given an input for each tick, fill in the table to show the next state. (b) What bit sequence(s) does this FSM recognize? Your answer should be a string of bits (ex. “01” or “1110”). 11 0- 10 00 01 Time 0 1 2 3 4 5 6 input START 1 0 0 1 1 0...
. On the design process of count-down in Excess-3 code using SR-FF which of the following answers are incorrect? The minterm numbers for each Flip Flop are: A B C D 9 1 1 0 0 8 1 0 1 1 7 1 0 1 0 D 6 0 0 1 HHHHHHHHH 5 1 0 0 0 4 0 1 1 1 1 1 3 0 0 2 0 0 0 0 0 2 0 0 19 1 9 0...
Part A Consider the table below. A, B, and C represent logic-variable input signals; F through K are outputs. (Figure 1) Using the sum-of-products approach, select an expression for G in terms of the inputs. O G ПМ(0,2,4,5) G m(2,3,4,5) G-m (1,3,6,7) O G_ⅡM(1,3,4,6) GEm(0,1,3) O G IIM(0,1,6,7) O G-En(2,4,5,6,7) O G m(0,2,5,7) 0 G=Σm(2,3,6,7) O G IIM (0,1,4,5) O G-ПМ(0,1,2,6,7) Figure 1 of 1 Submit Row A BC F G H IJ K Part B 0 0 00 1...
Assume a function F(a,b,c) is 0 when abc-010 or abc=101, and is 1 when abc are otherwise. Which Karnaugh-map correctly describes set of prime implicants for a minimum sum-of-products for the function F? C ab ab ab 00 00 00 01 01 10 11 11 10 11 10 3 2 1 O 1 only 2 only 03 only Both 1 and 2 are correct Both 1 and 3 are correct Both 2 and 3 are correct
The state diagram for a sequential circuit in shown below. Input X, Y Output Z 000,D 10/0, 11/0 01/1,11/0 00/0,01/0 01/1,10/1 00/1, 10/0 00/1, 11/1 10/0, 11/1 a) b) c) (4 pts) Find the state table (1 pt) Make a state assignment (3 pts) Find an optimized circuit implementation using SR FFs, NAND gates, and inverters.
AB 00 01 11 10 CD 00 0 0 4 1 12 1 8 1 01 1 1 5 1 13 1 9 1 11 3 1 7 0 15 0 11 0 10 2 0 6 0 14 0 10 1 Simplify F(A, B, C, D) using the zeros of the k-map to get F`, then use De Morgan’s formula to get F in product of sums and select the one that matches it from the following; a-...
multiple choices Question #4 • Determine the operation performed by the ALU for the given value of the select bits. S4 S3 S2 S1 SO = 10 110 OR 4-10-1 Mu MSB LSB TI S3 S2 NOT NAND Addition Subtractio 2-10-1 Mux S1 4-bit Addor Sum Cin Question #5 • Identify the static-1 hazard in the logic circuit given below. XX 0-4 4-5 5-7 0-1 None of the above. FIA,B,C) AB c 0001 11 10 Question #6 • Identify the...
use the matirces defined below for the following set of problems. Problem Set 5 Use the matrices defined below for the following set of problems. [2 3 C= 5 7 DE 23 A=3 B= 23 c= 57 D=23,8 E = 01 = (10 61 F= 0 2 3 (4 o o 5 6 91 1. Find: 1a) 3A 1b) A+B 1c) AB 1d) BC le) CB 1f) AE 1g) FF 1h) A+C 11) EF 11) 2B-8E 15