IIn the abve circuit the enable input is directly conneted to ground. So, the circuit is always in enable mode means it is enabled. The canonical SOP expression is
1. Provide the function table of a 3-to-8 active-low output decoder with active-low enable input. 2....
3. Consider a tri-state inverter with an active-high enable. (So the output of the buffer is enabled when the enable signal is high, and is in tri-state when the enable signal is low.) Complete the truth table. En A Out 0 0 0 1 10 AoOut En (active high) 4. Consider an open-collector buffer. Complete the truth table. A OU 1 AO-Out
Use 3-to-8 lines decoders to achieve the following: (Decoders should have one active-low ENABLE input, active-high binary code inputs, and active-low outputs. You can use additional gates) F = Σ A,B,C,D (2,4,6,14)
using 4 to 1 line multiplaxors that have tri-state outputs with an active low enable input,along with a 2 to 4 line active low output decoder, draw a schematic block diagram of a 16 to 1 multiplexor
1) The figure shown below shows how four 74xLS138s (3 to 8 Decoder) can be arranged to function as one-of-32 decoder. The decoders are labeled Zo to Z Answer the following: a. Which output will be activated for A 4As A2 Ai Ao 11101 b. What range of input codes will activate Z2? (MSB 123 :1 2 3 123 11 23 74ALS138 74ALS138 74ALS138 74ALS138 012345671 10123'4 5 6 71 10123A 5 6 7| |0123-4 5 6 7 Oni Os
1. i. Design and test a 3-to-8 decoder with active-low outputs using VHDL/HDL. Demonstrate your outputs in the BASYS board. (Note: Capture the pictures of your output and add in in your answer script) ii. Include (screenshot) VHDL codes and .xdc file modification in your answer script. ili. Develop a truth table following your outputs. (Note: You do not need to show step by step procedures, except what were asked in the questions]
Design the circuit for f(A,B,C,D)=ΠM(0,1,4,7,8,12-15),d(2,3,10) using a minimal number of 3-to-8 line decoders and NAND gates (any size). Decoder outputs must be active-low. Also, assume that the decoder has one active-high enable line G0. If you need NOT gates, you must show them in the diagram using NAND gates.
Question 3. M uw 4 2 prioeity encoder can be used to form 16-4pr ak ty encede b) For the 4-1 multiplexer shown in the figure below, find the Boolean epression of the output, F, and express it in simplest form. BOD- 4-1 Mux 1 c) Implement the above expression, F, using inverted output decoder (active low decoder). Question 3. M uw 4 2 prioeity encoder can be used to form 16-4pr ak ty encede b) For the 4-1 multiplexer...
Given the 3 lines to imes 7413s decoder IC s in Sgre 2 74138 YS Y4 P Y3 Y2- - G2A Figure 2. 74138 Decoder IC a) Fill the following truth table GI G2A G2B 0 X x 1 x X 1 CBA x X 1 0 00 1 0 0 1 1 1 0 0 1 10 5 marks b) Write the expressions ofoutputs y,,--, as functions of the inputs C, B, A c) Use this decoder and logic...
3) A digital circuit is shown input output input 4 input This circuit performs the function of a(n) (A) SR flip-flop (B) JK flip-flop (C) D flip-flop (D) T flip-flop 4) A digital circuit is shown inputs Y Z output no. 1 output no. 2 This circuit performs the function of a (A) 2-bit comparator (B) decoder (C) full-adder (D) full-subtractor
(18 pts) Given the Boolean function F(A, B, C, D) = Σ (0, 1, 2, 3, 4, 5, 7, 8, 10, 12, 14) a. Draw a Karnaugh Map. b. Identify the prime implicants of F. c. Identify all Essential Prime Implicants of F. d. Derive minimal SOP expressions for F e. Derive minimal POS expressions for F. f. Assume each inverter has a cost of 1, each 2-input NAND gate has a cost of 2, and 4-input NAND gate has...