Question

i know this solution, but can you please explain why and when to use the Tphl and when to use the Tplh for the inverter and Xor gate?

LAMDL 10 Quiz 1 3) for the circuit and specifications shown. Find the parameters a), b) Use the specs below for the XOR gate, inver CSE and Tip-flop Vc3.3V Vo: 36 ) La Cik — >> write the equations first, then fill in the numbers. a) What is the minimum clock period for the circuit shown above? 10 pts =16mn= TPCK A(Ff) + TPhilind+TP INCTUR) +Tsulff) = -2onsul b) What is the setup time requirement for the overall circuit as shown? 5 pts Tsu= Tsulff) + Tein (XOR) 6 = 705 e) What is the hold time requirement for the overall circuit as shown? 5 pts -_20s hold time الاميري Tomin (KOR) This Tulff) - Ovet 6 Flip-Flop Timing Specs: Symbol min typ Tsu Inverter Timing Specs: Symbol m in typ TPHL 1 2 1 1.5 max 3 2 units ns ns 0.5 max units ns 1 ns 1 ns 180 MHz TPLH TPCKO 0.5 Folk Test conditions: Vcc=5v, RIK, C =20 pF i Test conditions: Vcc=3.3v, R =1K, C =20 pF XOR Gate Timing Specs: Symbol min typ TPHL 2 3 2 3 max units 5 nS 6 ns TPLH Flip-Flop Timing Specs: Symbol m in typmax units Tsu TH Ons Теско 10 ns FCLK 60 MHz Test conditions: Vec-3.3V, RL - IK, CL-40 pF Test conditions: Vec-3.3V, RL = 1K, CL = 40 pF 47047501_1201.doc