Question

Hello

The question is to develop the waveform.

1) The verilog is below

C:/Users/ISHIMOTO/Documents/EEE_333_Homework/EEE333_Homework2/homework2_2.v - Default Ln# 1 module homework2_2 (output F, Fs, input A, B, C, D); 2 assign F=-A-B-C-D-A-B&C8-DI-AGB&-C&DI-AGB.C&D ABS-C&DAGB&CDA--B&-CS-DA-B&CDA--B&C&D; 3 assign Fs=BD B&-DA&B&C; 4 endmodule 5

2) Please show the testbench in order to develop the waveform.

Thank you for your time.

Answer 1

module homework2_2 (F, F3, A,B,C,D); input A,B,C,D; output F,F3; assign F= A&-B&-C&-D | A&-B&C&-D | A&B&-C&D | A&B&C&D | A&B&-C&D | A&B&C&D | A&-B&-C&-D | As-B&-C&D | As-B&C&-D ; assign F3=B&D B&-DA-B&C ; endmodule

); module Testbench_homework2_2 reg A,B,C,D; wire F, F3; homework2_2 H1 (F, F3, A,B,C,D); initial begin #10 A=1; B=1; C=1; D=1 ; #10 A=0; B=1; C=1; D=1 ; #10 A=1; B=0; C=0; D=1 ; #10 A=1; B=1; C=0; D=1 ; #10 A=1; B=1; C=1; D=0; #10 A=0; B=0; C=0; D=1 ; #10 A=0; B=1; C=0; D=1 ; #10 A=1; B=0; C=1; D=0; #10 A=0; B=0; C=0; D=0; #10 A=0; B=1; C=1; D=0; #10 A=1; B=0; C=0; D=0; #20 $finish; end endmodule

130.00 Name Value 10 ns 120 ns 40 ns 160 ns 180 ns 100 ns 120 ns ILUTLULUL TIL IRA 1 B 0 C 0 0 1 F Fs