Question

Bus A Bus B Bus C Bus D GRC I IR TERC GRD MAR TERO CMAR- Read- Write Address Memory Data out Data in F3 F2F1FO Action 0 0 0 0 B+1 0 001 B-1 0 0 1 0 B+C 0 0 1 1 B-C 0 1 0 0 C-B 0 1 0 1 C and B 0 1 1 0 Cor B | 1 | 1 | 1 B 0 0 0 C 0 0 1 C-1 010 C+1 01 | 1C*B 100 C/B 1101 Unused 1 1 1 0 Unused 1 1 1 1 Unused GORC MPLX MBR I ERC M_MBRT CBR GJORD 10 GPc_c MPLX PC IEMBRD Epcc CPC Goco M_PCT Incrementer TEpco MPLX TEro Gro GAOC MPLET MATT C - MPLXR O M_ROWCno - MPLXA 1 0 MPLX RO TEROC GAD GAC TERO M RATC GALO ERIC ALUCH TERLO IMPLXA В M_ALU_B VCNZEF CCR MPLX Cengage Learning 2014 M_ALU_A Cinnra 72

Answer 1

17.91 R14 R1+RO Steph. Load the address at tead of PC to MAR & issue READ signal. Epc_c, M.ALU. B=1, CMAR , READ Wait for Memory completion Cread) & receive the instruction in MBR Increment PC address to store the address of next instruction. Load instruction in LR. WFMC, M-MBR = 0, CMBR , CIR , M-PC=1, CPC step3 aften decoding sttrande the data of Ro to C and also transfen the data of R1 to B. Issue Btc. ERO-C, ERA-D, F3=0, F2=0, F1 =1, F0=0, M-ALU-A=0, stepy store the result in RI. M-R1=1, CRI: