Please Solve As soon as
Solve quickly I get you thumbs up directly
Thank's
Abdul-Rahim Taysir
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Counter_BCD IS
port( clk: in std_logic;
--data_in : in std_logic_vector(3 downto 0);
reset: in std_logic;
---load: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end Counter_BCD;
architecture logic of Counter_BCD is
COMPONENT BCD_1_digit IS
port( clk: in std_logic;
--data_in : in std_logic_vector(3 downto 0);
clear: in std_logic;
---load: in std_logic;
data_out: out std_logic_vector(3 downto 0)
);
END COMPONENT;
signal D : std_logic;
signal data1,data2: std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BCD_1_digit PORT MAP (
clk => clk,
clear => reset,
data_out => data1
);
uut1: BCD_1_digit PORT MAP (
clk => D,
clear => reset,
data_out => data2
);
process(clk,reset)
begin
if data1 = "1001" then
D<='1';
else
D<='0';
end if;
count <= data2 & data1;
end process;
end logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library ieee;
--use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY BCD_1_digit IS
port( clk: in std_logic;
--data_in : in std_logic_vector(3 downto 0);
clear: in std_logic;
---load: in std_logic;
data_out: out std_logic_vector(3 downto 0)
);
end BCD_1_digit;
architecture logic of BCD_1_digit is
begin
process(clk)
variable reg: std_logic_vector(3 downto 0):="0000";
begin
if (clk'event and clk = '1') then -- otherwise update the
states
if (clear = '1') then -- go to state zero if reset
reg:="0000";
else
if(reg = "1010") then
reg:="0000";
else
reg:=reg+1;
end if;
reg:=reg;
end if;
else
null;
end if;
data_out<=reg;
end process;
end logic;
-- testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_counter IS
END tb_counter;
ARCHITECTURE behavior1 OF tb_counter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Counter_BCD IS
port( clk: in std_logic;
--data_in : in std_logic_vector(3 downto 0);
reset: in std_logic;
---load: in std_logic;
count: out std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic ;
signal reset : std_logic ;
--Outputs
signal count : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Counter_BCD PORT MAP (
clk => clk,
reset => reset,
count => count
);
-- Stimulus process
stim_proc: process
begin
clk <='0';reset<='0';
wait for 10ns;
clk<='1'; reset<='1';
wait for 10ns;
reset<='0';
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
wait for 10ns;
clk<='1';
wait for 10ns;
clk<='0';
end process;
end behavior1;
Please Solve As soon as Solve quickly I get you thumbs up directly Thank's Abdul-Rahim Taysir...
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