Question

6.(10pts) Using a graph illustrate tf and tr and the propagation delays PHL and tPLH for an inverter gate. Which FET is responsible for tphl and which one for tlh ?

show full solution please, practice exam.

Answer 1

Graph illustrating Rise time, Fall time & propagation delays Vон 90% 50% {(VOL + VoH) 10% - VOL I PLH {PHLF Vон 90% -50% {(VOL+ VoH) 10% VOL

In the above graph for a CMOS inverter gate,

t_r --> Rise time

t_t --> Fall time

t_PHL --> High to low Propagation delay

t_PLH --> Low to high Propagation delay

The first one is the graph of Input voltage and the second one is Output voltage over time.

The propagation delay is defined as the time taken at which input is 50% of its logic value to reach the output to its 50% of its logic value.

When the input is going from low to high, then the delay define above will be t_PLH or t_PHL otherwise as shown in the figure.

The Propagation delays are measured between 50% values of input and output Waveforms.

The total propagation delay is,

t_p = (t_PHL + t_PLH) /2

Rise time t_r is defined as the time taken for the input to reach 90% of the logic value from 10%.

Incase of output, it is called as Transition time low to high t_TLH.

Fall time t_f is defined as the time taken for the input to reach 10% of the logic value from 90%.

Incase of output, it is defined as Transition time high to low t_THL.

For example, to the inverter shown below

VDD CMOS Inverter Qp ipp |iDN QN

NMOS Q_N is responsible for the output going from high to low or to be low. So NMOS is responsible for t_PHL

PMOS Q_p is responsible for the output going from low to high or to be high.So PMOS is responsible for t_PLH.