Question

(a) A negative-level sensitive (negative triggered) D latch circuit can be designed using a circuit as shown in Figure 3 CLK DH CLK ola CLK Figure 3 Obtain the equation for the output of the circuit, Q. Analyse the circuit and determine when the circuit is in 'transparent form and "opaque' form with regards to the clock input. Assess the output at these two forms. (ii) Modify the circuit to produce a positive-level sensitive (positive triggered) D latch. Draw and clearly label the new circuit and state the new equation for the output.

Answer 1

lo 99 Tuk before analyning the cht let's see the tranmission gate alone. A T B В B G= AB és A=1 ET high if Azo А C positive level of the clock) then that T2 will be and 9 well book live Now ég clu = r can observe out So cht well T دکے can say that from ther o well maintain as long as thes clx-1 above diagram étra previous state es valid and the 9p. untill ckt this is clr o Now and 92 CKA will then T, will ве on/active Gb / en active. In that case the will be look like. D 4 So Q =D and ł =D as long as cluso

The the lp of cercut és equath bor Ont, s cek. On t can D here of 9 present state next state Chti os IP to ckf elp claw signal. alk D epp 이P the the long "transparent form clk -o cht passes thes mode thes boom یک called es and at the %P cla - O a= D 761 eie transparent room اد et's pass che o/P the cht doesn't thes state ob the and at this time és retained. but clk 1 then present elp to So és called "opaque" form previous state ou circuit enei the et cler = 1 die oraqш Gom 3 alk ol Ti clk UK A Dlatch has been drawn positive abore thes level sensitive mill nore et clk 1 anti =D ca Onni =on

D عظ علاما & well and ef cle=1 will be active on well be , cie off Po transfering lp if clu = and off / inactive be on/active. that maintain the state of Pp. finally the olp ean Gor the positive level D latch will al genen be Onti к D + can on So CIK =1 ig TAR clo=0
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