Question

5) A single-input (x) single-output(z) synchronous sequential circuit is required to operate as follows: i) The circuit is put to a specific initial state (call this state A) ii) Starting from state A, the circuit will give a 1 output when the input sequence up to and including the present time contains an odd number of 0's and an odd number of l's: the circuit will give a 0 output at all other times An example input and corresponding output sequence is shown below x: 0010110101111001010100110...... z: 0001010001010001000101010... Design the sequential circuit given above using T flip flops and external gates.

Answer 1

The excitation table of T-Flip Flop.

Q	Q+	T
0	0	0
0	1	1
1	0	1
1	1	0

STATE DIAGRAM.

A (00) - represents 0's even and 1's even

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B(01) - represents 0's even and 1's odd

C(10) - represents 0's odd and 1's even

D(11) - represents 0's odd and 1's odd.

State table

Q1	Q0	X	Q1+	Q0+	T1	T0	Z
0	0	0	1	0	1	0	0
0	0	1	0	1	0	1	0
0	1	0	1	1	1	0	1
0	1	1	0	0	0	1	0
1	0	0	0	0	1	0	0
1	0	1	1	1	0	1	1
1	1	0	0	1	1	0	0
1	1	1	1	0	0	1	0

K-MAPS

Q1 Q0	00	01	11	10
X=0	0	1	3	2
X=1	4	5	7	6

FOR T1

Q1 Q0	00	01	11	10
X=0	1	0	0	1
X=1	1	0	0	1

mapping quad 0,2,4,6

T1 = Q0' ( compliment of Q0)

FOR T0

Q1 Q0	00	01	11	10
X=0	0	1	1	0
X=1	0	1	1	0

mapping 1,3,5,7

T0 = Q0

FOR Z

Q1 Q0	00	01	11	10
X=0	0	0	0	1
X=1	0	1	0	0

Z = X' Q1 Q0' + X Q1' Q0.

CIRCUIT DIAGRAM

U1 U2 SET SET T CLK 0 CLK RESET RESET CLK TFF TFF 10Hz 03 U6A U5 AND3 7404N х Z U4 OR2 AND3 Design1*

At left, T0 flip flop and right one is T1 Flip flop.

THANK YOU