Question

For the SAM array in question 1, design three one-stage or multi-stage row decoders, and using logical effort theory determine which one has the lowest minimum delay. Assume the input capacitor of each SRAM memory cell is three times larger than that of a minimum-sized NMOS, and the m allowed input capacito

Question 1:

In detail and show and explain all steps

Digital Electronics

Answer 1

Answer

Question 1

area of 32-bit word

= 32*2μm by 4μm

= 64μm by 4μm

we see that the length is 16 time height....ie (2⁴ : 1) ratio of length to height

therefore for square layout format we must have 2⁴ rows for 1 word in a row

so in order to layout 2¹² words in square format

if there are 2^N words in a row we must have 2^N+4 rows in square format

total words in this format = (no.of words in a row)*(No of rows) = 2^N x 2^N+4 = 2^2N+4 = 2¹²

= 2N+4 = 12

= N = 4

therefore there are 2⁴ = 16 words in a row

and there are 2⁴⁺⁴ = 2⁸ = 256 rows

the area of the SRAM is (64*16μm) by (4*256μm)

= 1024μm by 1024μm

for 2^N outputs of a decoder there are N inputs

therefore

for column decoder

there are 2⁴ outputs of decoder

hence 4 inputs

for row decoder

there are 2⁸ outputs of decoder

hence 8 inputs