Question

a. Sketch a transistor layout, and Euler path, and a stick diagram for each of the following Boolean functions. You may assume that you have literals and inverted literals available as input to your gates. i. Y=AB + C ii. Y=(AB + C + DE) ii Y - ((A+B+C)(D+E)F) iv. Y- BD+ BC+ABC vi. Y- AB+BC +AC Our process (roughly speaking) is a 0.6μ process meaning the minimum channel length is 0.6μ. The gate oxidethickness is around 135A, and廿io mobility of tho ekotrens is 469cr/n/.s. . I nominal threshold voltage is 0.77v. K, for an nmos device is 57.9 μA/ The dopant level for an nmos device is NA-2.7x1017 cm3 b. i. Plot Ids for an nmos device with W= 1.5 μ, min channel length, and Vgs Consider the) impact voltage. Plot the change in threshold voltage as the substrate bias voltage changes from 0v to 5v. 0, 1, 2, 3, 4, and 5v ii. tho body cif)(尤€)n tho thiesheld ii. What is the gate capacitance per micron of gate width in this process?

Answer 1