Question

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Part A: Using sequential analysis and design tools introduced in this course, derive the cycle of a counter whose 4-bit inputs (A=Most Significant Bit; D=Least Significant Bit) are given in the following table and whose initial state is 1. 1 1 1 1 SA RA 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0 1 1 SB RB 0 X 0 X 0 X 0 0 0 X 0 X 0 X 0 0 1 Sc Rc 1 0 0 0 X 0 0 0 X 0 0 1 0 0 1 1 SD RD X 0 0 0 X 0 0 0 X 0 X 0 X 0 X 0 1 1 1 1 1 Note: Show clearly all the steps leading to your result. Results without supporting derivation/work/steps will lead to zero.

Answer 1

Am) Now the counter excitation table. cjele wou be designed from the given SR Flip flop excitation table NS S R PS O O 0 XO-oh O-OX o хо Porosent state A B .CD SA RA Next state A+ B+ ct Di SB RB Sc Ri SD RD 0 X ох хо O - 0 0 1 1 Х 10 0 1 - o 10. OO ох хо - O ох - ola 1 1 0 хо O - 010 I 0 OT - 1 11 10 — 0 0 1 0 1 0 - 0 I OLI хо ох 10 ох хо o X xo 10 хо 0 0 1 хо хо x O 1 0 хо 0 1 0 0 X I 1 1 0 1 - OOO!

Now the sequence of counting from poresent state overed next state is 0 4 6 3 10 13 15 So the counting sequence 1,3,4,6,7,8, 10, 11, 13, 15, 1,3,4,6 repeaks cons continously. -