Question

Instructions The answers to questions below must be written in the file named you MUST replace which has been provided with this test. Important: login the FSUl of the filename with you actual FSU login ID. That file has lines that begin with Question N. where N corresponds to the question number. Below or beside each Question N. there are placeholder as described must be replaced with the correct answer in the specific formats, below question Questions 1 and 2: find out all hazards that exist in the two separate code segments, one for each question. Within the answers file, and under each question write the hazards you have detected for that segment by replacing the x and Y with line numbers from the code segment, and Twith the type of solution to the hazard. T can be M, W or S, where M forward from Memory stage, W forward from Writeback stage, and s stall. that a hazard may need to be solved by a combination of stall and forwarding, in which case both have to be listed individually, For example, if you think there is a hazard between lines 1 and 4 of the code segment in question 1, which can be solved by stalling the pipeline and also forwarding from the Memory stage, you would write the following in the answers Question 1. For more hazards detected for that segment, simply create more lines under that segment in the answers file and follow this format. Question 1 add and $s1 $s2 St2 $s5, $s1 or $s 1. $s6 Question 2. 40 ($0) $s0, $s1 and stl, $s4, $12, $50, $s5 sub Questions 3 4: are based on the pipelined MIPS processor, which is running the following program and has a hazard detection unit-also note that the program may need stalls for correct execution. For each question the answer must be a comma- separated list of register names. For example if the answer to question 3 is registers St0 and St1, then the answer for that question must be written by replacing X on a single line Question stl ere is only one register for the answer, just write only the specific register name in

Computer science organization and architecture! Help!

Answer 1

Solution:

Note: multiple questions, please post separately

Question 1:

• There is clear data hazard between 1-2, 1-3 and 1-4 of the code segment.
• The data is written into the register s1 in line 1 but it is used by both line 2, 3 and 4.
• Thus there is occurs a data hazard.
• Formally the above detected hazards can be represented as given below.
• 1 2 S
• 1 2 W
• For instructions 1 and 2, they are consecutive instructions, so the data forward should be from write back stage.
• 1 3 S
• 1 3 M
• For 1 and 3 instructions, the data will be in memory, so the memory forwarding is enough to handle the hazards here.
• 1 4 S
• 1 4 M
• For 1 and 4^th instruction also the data forwarding from memory stage is enough to handle the hazards.

Question 2:

• In this case the same set of hazards occurs.
• The data loaded into register s0 will be used in the instructions 2, 3 and 4.
• There should be stall to execute the first instruction, the data forwarding will occurs.
• The same set of forwarding and stall will follows in this case also.
• Thus the forwarding sequences will be;
• 1 2 S
• 1 2 W
• 1 3 S
• 1 3 M
• 1 4 S
• 1 4 M

Question 3:

Answer: $t4

Explanation:

• For the pipelined execution of instructions, the instruction execution stages will be divided into stages and continuous execution will takes place.
• That means in first 5 cycles of the pipeline the first instruction will be completed its execution and the second instruction might complete 4 steps also.
• For the given question the registers being written are first one surely register t4.
• Since data forwarding is used to avoid data hazards, the register t0 in the second instruction needs the value of t4.

Question 4:

Answer: $t4, $s0

Explanation:

• As given above the date written at t4 can be readily read by second instruction due to data forwarding.
• Surely register s0 also.