Question

3. For the ECL gate shown in the following sketch, the output is Y and the input is A Rc 7S2 Q5 VRE 02 AQ 50Ω D2 5.2V

Answer 1

Circuit diagram of two input ECL OR/NOR gate. \r\n Transistor Q_2 and Q_1A form differential amplifies. Transistors Q_1A and Q_1B are in parallel. Transistors Q_3 and Q_4 are emitter followers whose emitter voltages are same as base voltages Inputs are applies to Q_1A and Q_1B and Q_2 is supplied with constant -1.3 v. When the inputs A and B are both low i.e., -1.7 v Q_2 is forward biased than Q_1A and Q_1B. So Q_2 is ON and Q_1A and Q_1B and OFF. The value of R_2 is such that current flowing through Q_2 puts the collector at about - 0.9 v. Emitter of Q_4 is at -0.9 - 0.8 = -1.7 v, and so, OR output is low. Base current of Q_3 passing through R_1 is very small value of R_1 is such that this current puts collectors Q_1A and Q_1B at about -0.1 v. So, emitter of Q_3 is at -0.1 - 0.8 = -0.9
Different types of transistor circuits are emitter follower, differential amplifier in ECL devices