Question

Design a CMOS gate implementing the function F = ((?*?)+?) (with a NOT over the whole equation) . The channel length of all transistors is L=1μ and the output load capacitance is CL = 1pF. The width of all nMOSFETs is Wn and all pMOSFETs Wp.

(a) Calculate Wn and Wp so that that the worst-case propagation delay times are tPHL = tPLH =1ns. Take VDD = 5V, VTN0 =1V, k’n = 60μA/V2, VTP0 = -1V, k’p = -25μA/V2.

solution: Wn = 11.20 μ and Wp = 26.88 μ

(b) Assuming all inputs are equally likely to be high or low, calculate the dynamic power dissipation Pdyn as a function of the operation frequency f

solution: Pdyn = (0.625)(0.375)xCLVDDf = 1.17x10-12f Watts.

(c) Calculate the maximum frequency of operation, and hence the maximum dynamic power dissipation.

solution: fmax = 0.5tP where tP = 0.5 (tPHL + tPLH) = 1ns  Pdynmax = 0.585 mW

Answer 1

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