Mos transistor Given a combinational logic circuit as shown in Figure Q3 Output NOT Gates A...
Question 10 (5 marks) A combinational logic circuit is shown in Figure 3 along with a timing diagram. a) The output waveform (X) shown in the timing diagram is not correct for the circuit shown. Draw the correct waveform. (2 marks) b) The output waveform shown is the result of incorrect implementation of the circuit gates has been replaced by another type of gate. Which gate has been replaced and what is the replacement gate? Explain your answer. (3 marks)...
QUESTION 1 B. A В. F E (a) (b) Figure 1 Consider the combinational logic circuits shown in Figure 1 (a) and Figure 1 (b). Prove that the two-logic circuit functions the same where the output expression, E equals the output expression, F; given the same inputs (A, B and C). [10 marks]
using all D flip-flops and combinational logic (AND/OR/NOT gates only) b) using all T flip-flops and a multiplexer of size 8:1 Problem 3: (10 pts) Design a synchronous machine (Transition Table, K-maps, Final Equations, Circuit Diagram) that counts through the following sequence in the order shown below. Note, there are no inputs or output variables, so your Q values must reflect the Hex value listed B 74 2 D9 3 0 and repeat a) using all D flip-flops and combinational...
QUESTION 1 B A. B. F E (a) (b) Figure 1 Consider the combinational logic circuits shown in Figure 1 (a) and Figure 1 (b). Prove that the two-logic circuit functions the same where the output expression, E equals the output expression, F; given the same inputs (A, B and C). [10 marks) QUESTION 2 The following program is written in the assembly language of 8085 processor: LXIB, 20DF LXI H, 2B44 MOVA, C SUB B MOVAL ADDH INX B...
Q6. a) Write the output expression for the circuit shown in the figure. b) Develop truth table for the circuit. (1 Mark) (4 Marks) A B C 13 X D Fig.2 07 [5] a) Minimize the following logic function using K-Map. b) Implement the minimized expression using basic gates. (3 Marks) (2 Marks) F(A,B,C,D) = (0,2,5,7,8,10,13,15) Q8 a) Write the output expression of the logic circuit shown in the figure. b) Minimize the expression using Boolean laws and theorems. C)...
Design a combinational logic circuit which has one output Z and a 4-bit input ABCD representing a binary number. Z should be 1 iff the input is at least 5, but is no greater than 11. Use one OR gate (three inputs) and three AND gates (with no more than three inputs each). Using K-map, find min SOP and min POS form for the outputs W, X
The layout of a CMOS complex logic circuit is given in the Figure 1. 4. Draw the corresponding circuit diagram; and (10 Marks) a. b. Colculate the W/Doivalent of all the nMOS and PMOS transistors for simultaneous switching of all the inputs, assuming that (W/, 25 for all MOS transistors and (W/, 20 for al nMOS transistors. (10 Marks) FIA, B,C,D,E ) A B Figure 1 The layout of a CMOS complex logic circuit is given in the Figure 1....
Figure 1 shows a logic circuit with output F. A с D F B Figure 1 (a) Without simplification, determine the logic expression for F. (b) Simplify the expression using Boolean algebra. (c) Sketch the output waveform, F in Figure 2. A B с F Figure 2
PROBLEM 3 (16 PTS) ▪ With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by: PROBLEM 3 (16 PTS) • With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by: Qit+1) + y + Q(t) + y(t) (4 pts) • Complete the timing diagram of the circuit whose VHDL description is shown below. Also, get the excitation equation for q. library ieee: elsaf (cll'event and clk...
solve both 2.10 Find the transistor schematic for the CMOS logic circuit realized by the layout shown in Fig. P2.10. Give the widths of all transistors. AssumeL = 21, where A = 0.4 um. In tabular form, give the area and perimeter of each junction that is not connected to VDD or to ground. VDD Polysilicon 8A n well -p diffusion Active region Out 6/ n diffusion Metal Gnd A Fig. P2.10 D 17.33 The circuit of Fig. P17.33 consists...