Question

A byte-addressable memory system contains four memory modules each of which is 32 bits wide by 2^28 cells deep. The system employs a 1 MB 2-way set associative cache with 128-byte cache lines. It also uses a 32-bit CPU-to-memory data bus as well as 32-bit physical addresses. Each memory module requires 4 clock cycles to perform either a read or a write operation.

a) Assuming that the memory system is low order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each field in bits. Also describe how each field is used.

b) Assuming that the memory system is high order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each field in bits. Also describe how each field is used.

c) What is the minimum number of clock cycles required to fill a cache line if the memory system is low order interleaved?

d) What is the minimum number of clock cycles required to fill a cache line if the memory system is high order interleaved?

Answer 1

There are 128 lines in the cache. Thus the cache consists of 64 sets of 2 lines each. Therefore 6 bits are needed to identify the set number. For the 1-Mbyte main memory, a 20-bit address is needed. Main memory consists of 1-Mbyte/128 bytes = 2¹⁹blocks. Therefore, the set plus tag lengths must be 19 bits, so the tag length is 13 bits and the word field length is 13 bits. Our 32-bit address is now broken up as follows:

a)

Bits 0-12 indicate the word offset

Bits 13-18 indicate the cache set

Bits 19-31 indicate the tag

b)

Bits 19-31 indicate the word offset

Bits 13-18 indicate the cache set

Bits 0-12 indicate the tag

c) 16 clock cycles required to fill a cache line if the memory system is low order interleaved.

d) 16 clock cycles required to fill a cache line if the memory system is high order interleaved