Question

A system has four sensors that can produce an output of 0 or 1. The system...

A system has four sensors that can produce an output of 0 or 1. The system operates normally (no alarm) when exactly one or none of the sensors have output equal to 1. An alarm must be raised when two or more sensors have the output of 1.

Design the simplest circuit that can be used to raise the alarm.

a) Derive the general equation for an alarm function ? where ? is true when the alarm is raised, and the sensor inputs are ?1, ?2, ?3, ?4. Show a Karnaugh map to derive a simplified POS or SOP form for the function ? .

b) Write a VHDL program to Implement the function ?.

c) From the equation derived in (a), determine a general pattern and describe it. Use this pattern to determine an equation to implement
a seven-input alarm system with sensor inputs ?1, ?2, ?3, ?4, ?5, ?6, ?7 and output ?. Write a VHDL program to Implement the expanded alarm in VHDL.
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Answer #1

INPUT

OUTPUT

X4

X3

X2

X1

F

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

1

0

1

0

0

0

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

0

0

0

0

1

0

0

1

1

1

0

1

0

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

b)

library ieee;
use ieee.std_logic_1164.all;

entity circuit is
   port (   X4, X3, X2, X1   : in std_logic;
       F       : out std_logic
   );
end circuit;

architecture arch of circuit is

begin

   F <= (X4 and X3) or (X4 and X2) or (X4 and X1) or (X3 and X2) or (X3 and X1) or (X2 and X1);
  

end arch;

c) pattern is used in the data flow statement

library ieee;
use ieee.std_logic_1164.all;

entity circuit is
   port (   X7, X6, X5, X4, X3, X2, X1   : in std_logic;
       F               : out std_logic
   );
end circuit;

architecture arch of circuit is

begin

   F <=    (X7 and X6) or (X7 and X5) or (X7 and X4) or (X7 and X3) or (X7 and X2) or (X7 and X1) or
       (X6 and X5) or (X6 and X4) or (X6 and X3) or (X6 and X2) or (X6 and X1) or
       (X5 and X4) or (X5 and X3) or (X5 and X2) or (X5 and X1) or
       (X4 and X3) or (X4 and X2) or (X4 and X1) or
       (X3 and X2) or (X3 and X1) or
       (X2 and X1);
  

end arch;

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