step 1 we have to make a table.
the variables which are connected to the select lines forms the column headings to the table and the variables which are not connected to the selects lines forms the row heading.
in this case BCD is connected to select line,since we have 3 select lines so we will have 2^3 = 8 input lines. so the no. of rows of the table = 8.
as shown in figure.
step 2 calculate the corresponding decimal value as shown in table and fill in the table.(as show in above figure).
step 3 encircle the numbers in the table with max-terms given in the question i.e. £(1,3,4,11,12,13,14,15) shown in the figure.
step 4 calculate the inputs to the multiplexer by following rules:
i) if out of 2 rows none of the digit is encircle........enter '0'.
ii) if both the rows are encircled .........enter '1'
iii) if one is encircle fill the corresponding row value i.e either A or A'.
step 5 now construct the multiplexer as shown in the figure.
F(ABCD)=£(1,3,4,11,12,13,14,15) using 8x1 MUX with A as an input variable and and BCD as selectors
3. (10 pts, Ch 2 & 6.2] For the 8X1 MUX below, complete the following: a. [4 points, Ch 2] Fill in the truth table. 8x1 ABCD | 0 0 0 0 0 0 1 0 0 101 0011 0 1 0 0 0 1 0 1 0 1 100 01111 1000 1 0011 1010 1 0 1 1 1100 11 01 AB.CD) MUX s2 s1 s0 b. (3 points, Ch 6.2] Using the blank K-map below, provide the Minimized...
d) e) f) g) Draw block diagram of a 8x1 multiplexer (mux), obtain truth table and write VHDL code. Draw block diagram of a 1x8 demultiplexer (demux), obtain truth table and write VHDL code Draw block diagram of a 3x8 decoder, obtain truth table and write VHDL code Draw block diagram of a 8x3 priority encoder, obtain truth table and write VHDL code.
2. A 2xl mux has two single-bit inputs and one selector bit (S). Such a mux allows you to choose one of the single-bit inputs to appear at the output. Let's say, you want to use four 2x1 such multiplexers to construct a 4-bit 2X1 multiplexer with selector (S). Such a multiplexer can be used to choose among four 4-bit inputs (see figure below). If A, B are all 4-bit inputs and are connected to the inputs of the multiplexer....
Design a 32-input Mux using 8 and 4 input multiplexers. Design 4 to 16 decoder using 3 to 8 decoders. 6.
3) (10 points) Implement F(A, B, C) = m(0,1,4,7) using an 2-to-1 MUX (use the symbol) and any other basic logic gates necessary (AND, OR, or NOT gates). Show the truth table and minimize any combinational logic (other than the MUX) in sum-of-products form. Use the left most input(s) for the MUX select input(s) in your schematic.
A multiplexer (MUX) is a logic function that combines several inputs and a control input, the output of which is one of the inputs selected by the control input. A2-1 MUX is shown below: Where X and Y are inputs and S is the control input. The Truth Table of the 2-1 MUX is given by: Show that the 2-1 MUX forms a complete set of logic functions by realizing a NOR gate using only 2-1 MUXes.
Q31 For the figure shown below W is an input, (X, Y and Z) are connected to (S2, S and So), find the Boolean function F (W, X, Y, Z) in SOP and implement it use: 1. Multiplexer: One-piece (4 to 1) and external gates (W, X are selectors). 2. Decoder: Five (2 to 4) with AND gate. 0 1 8 to 1 MUX Do D, F OP D, S S S 35 Marks] X Y Z
Q31 For the...
Q.3-A). The circuit of Figure below shows how an eight-input MUX can be used to generate a four-variable logic function, even though the MUX has only three SELECT inputs. (a) Set up a truth table showing the output Z for the 16 possible combinations of input variables. b) Write the sum-of-products expression for Z and simplify it. 45 V 74HC151 MUX
Build the Boolean function F(W, X, Y, Z) = ∑ (1,3,4,11,12,13,14,15) using a) a 8x1 multiplexer and external gates. b) a 4x1 multiplexer and external gates. c) two 3-to-8 decoders with enables and external gates with a maximum of 4 inputs.
2. For the circuit shown below, using ABCD matrix determine a. The input impedance b. The output impedance R 502 Vg Zo1 50o 1000 1-10 + j50Ω 2