library ieee;
use ieee.std_logic_1164.all;
entity mux8x1_design is
port (
I0, I1, I2, I3, I4, I5, I6, I7 : in std_logic ;
Sel2, Sel1, Sel0 : in std_logic;
Out1
: out std_logic
);
end mux8x1_design;
architecture behavioural of mux8x1_design is
signal temp_sel : std_logic_vector(2 downto 0);
begin
temp_sel <= Sel2 & Sel1 & Sel0;
process (I0, I1, I2, I3, I4, I5, I6, I7, temp_sel)
begin
if (temp_sel = "000") then
out1 <= I0;
elsif (temp_sel = "001") then
Out1 <= I1;
elsif (temp_sel = "010") then
Out1 <= I2;
elsif (temp_sel = "011") then
Out1 <= I3;
elsif (temp_sel = "100") then
Out1 <= I4;
elsif (temp_sel = "101") then
Out1 <= I5;
elsif (temp_sel = "110") then
Out1 <= I6;
else
Out1 <= I7;
end if;
end
end behavioural;
// Demux
library ieee;
use ieee.std_logic_1164.all;
entity demux1x8_design is
port (
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 : out std_logic;
Sel2, Sel1, Sel0 : in std_logic;
I
: in std_logic_vector
);
end demux1x8_design;
architecture behavioural of demux1x8_design is
begin
temp_sel <= Sel2 & Sel1 & Sel0;
process (I, temp_sel)
begin
if (temp_sel = "000") then
Y0 <= I;
elsif (temp_sel = "001") then
Y1 <= I;
elsif (temp_sel = "010") then
Y2 <= I;
elsif (temp_sel = "011") then
Y3 <= I;
elsif (temp_sel = "100") then
Y4 <= I;
elsif (temp_sel = "101") then
Y5 <= I;
elsif (temp_sel = "110") then
Y6 <= I;
else
Y7 <= I;
end if;
end
end behavioural;
// Decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( sel2, sel1, sel0 : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7
downto 0));
end decoder;
architecture Behavioral of decoder is
signal temp_sel : std_logic_vector (2 downto 0);
begin
temp_sel <= sel2 & sel1 & sel0;
with sel select
y <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end Behavioral
//Priority Encoder;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity prioencoder8to3v is
port(
In1 : in STD_LOGIC_VECTOR(7 downto 0);
Y : out STD_LOGIC_VECTOR(2 downto 0)
);
end prioencoder8to3v;
architecture encoder8to3_arc of prioencoder8to3v is
begin
process (In1)
begin
if (In1(7) = '1') then
Y <= "111";
elsif (In1(6) = '1') then
Y <= "110";;
elsif (In1(5) = '1') then
Y <= "101";;
elsif (In1(4) = '1') then
Y <= "100";;
elsif (In1(3) = '1') then
Y <= "011";
elsif (In1(2) = '1') then
Y <= "010";;
elsif (In1(1) = '1') then
Y <= "001";;
else
Y <= "000";
end if;
end
end encoder8to3_arc;
d) e) f) g) Draw block diagram of a 8x1 multiplexer (mux), obtain truth table and...
A combination circuit is specified by the following Boolean functions listed below. h(a, b, c) = b,c' + a'c Implement the circuit with a 3x8 decoder. Provide truth table and drawing the logic/circuit diagram. Use the block diagram for the decoder provided in Figure A4 in supplements. Please label the inputs and outputs clearly. Note: use single 3x8 decoder Question 2 (15 points] A priority encoder is an encoder circuit that includes the Truth Table of a priority function. The...
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QUESTION 2 (40 MARKS) Figure Q2 show Binary to Gray code converter block diagram. Based on that figure, design: (a) Circuit using logic gates. Obtain the truth table and represent Yo, Y1, Y2 and Y3 in minimized SOP Boolean algebra term. Draw the circuit using logic gates (CO2:P03 - 20 Marks) (b) Circuit using 8 to 1 Multiplexer with A, B, C as a data selector. Obtain the truth table of each multiplexer. Draw the circuit using 8 to 1...
2) For an 8:3 priority encoder: a) Draw the schematic. b) Write the truth table. c) Write the Boolean expressions for each of the outputs in terms of the inputs. d) Draw the logic circuit for the outputs in terms of the inputs.
(20 pts)VHDL. Implement the logic circuit specified in the following truth table by using a 4:1 mulitiplexer ome regular logic gates. 11 Draw a schematic of your implementation. 2) Suppose that you are given the following VHDL code of a 4:1 multiplexer. Please write a VHDL code to describe your implementation by using structure modeling technique, by using the following 4:1 multiplexer asia your answer component in your structure modeling. Note that you do not need to re-write the following...
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(a) The truth table below shows a certain function
F(P,Q,R,S).
Implement the function F using an 8:1 multiplexer, without any
other logic gate. Only the constants 0 and 1, and the literals (but
not their complements) are available.
Fill in the inputs in the multiplexer diagram.
(b). Implement the function F
using a 24 decoder and a 4:1 multiplexer, and at most one logic
gate. Only the constants 0 and 1, and the literals (but not their
complements) are available....
Draw a circuit diagram for an encoder given the following table: A B C D E F G H S2 S1 S0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0...
design a state diagram that detects 7 bit ascii code of the last alphabet of your full name from a sequence of incoming bits.Derive truth table and draw circuit diagram of the system using d-flip flopsThe name is "Mr Master" or the last aphabet is"r"
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