Question

1. Write the Boolean expression for each output from the PLA below: F = F G H 2. Draw the block diagram (not logic gates) and the truth table for a 4-1 multiplexer. Label all inputs, outputs and select lines. 3. Explain the problem with the S-R latch and how it is fixed by the J-K flip-flop

Answer 1

1.

F = A'B' + ABC

G = A'B'C' + AB + BC

H = A'B' + C

2.

Со | 0 | 0 0 1 м | X0 x1 4:1 MUX X2 I x3

3)

Due to manufacturing methods, one gate will always win, but it's impossible to tell which it will be for a particular device from an assembly line. The state of S = R = 1 is therefore "illegal" and should never be entered.

The input condition of J=K=1, gives an output inverting the output state. However, the outputs are the same when one tests the circuit practically.

4)

o o o o o 1 о то от 1 1 o o 1 1 1 1 о 1

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