Question

Write a VHDL program for Full-Adder. You should firstly write down the Boolean algebra expression

of SoP of the Sum and Carryout in terms of in1, in2 and Carryin and then simplify them. Use the

following abbreviations for the declaration in your answer:

Sum= S

Carryin = C

In1= A

In2= B

Carryout = Co

Compile and simulate using modelsim or others. Print out the waveforms of A, B, C, S and Co using

the ‘wave’ in the modelsim (or others). Your waveforms/time diagram should cover all the

combinations of A, B and C.

3. Re-do the VHDL program but use the ‘variable’ and ‘process’

Print out the waveforms of A, B, C, S and Co to confirm your program.

Answer 1

Boolean Algebra Expression for SUM:
= A’ B’ C + A’ B C’ + A B’ C’ + A B C
= C (A’ B’ + A B) + C’ (A’ B + A B’)
= C XOR (A XOR B)
= (1,2,4,7)

Boolean Algebra Expression for Carry-OUT:
= A’ B C + A B’ C+ A B C’ + A B C
= A B + B C+ A C
= (3,5,6,7)

VHDL Program for full Adder:

module Full_Adder( 
  input A, B, C, 
  output S, Co
  );  
    reg[1:0] temp;
   always @(*)
   begin 
   temp = {1'b0,A} + {1'b0,X2}+{1'b0,C};
   end 
   assign S = temp[0];
   assign Co = temp[1];
endmodule  
// fpga4student.com 
// FPGA projects, VHDL projects, Verilog projects 
// Verilog code for full adder 
// Testbench code of the behavioral code for full adder 
`timescale 10ns/ 10ps;
module Testbench_Behavioral_adder();
 reg A,B,C;
 wire S,Co;  
 //Verilog code for the structural full adder 
 Full_Adder_Behavioral_Verilog Behavioral_adder(
    .A(A),
    .B(B),
    .C(C),
    .S(S),
    .Co(Co) 
   );
 initial begin
   A = 0;
   B = 0;
   C = 0;
   #5;
   A = 0;
   B = 0;
   C = 1;
   #5;  
   A = 0;
   B = 1;
   C = 0;
   #5;
   A = 0;
   B = 1;
   C = 1;
   #5;
   A = 1;
   B = 0;
   C = 0;
   #5;
   A = 1;
   B = 0;
   C = 1;
   #5;
   A = 1;
   B = 1;
   C = 0;
   #5;  
   A = 1;
   B = 1;
   C = 1;
   #5;  
  end
      
endmodule 

The wave diagram is as follows: