Question

In VHDL, what is the sensitivity list used in a Process? How does this effect when the process is evaluated?

Answer 1

Answer)

The sensitivity liste here is defined to be a compact way for specifying the set of signals, or the events which can resume a process and this is also specified better after the keyword process is implemented. This is also equivalent to the wait on the statement that is the last statement of the process statement section.

When considering the process sensitivity list, it helps to declare the signal which is the process that is sensitive and the process gets evaluated in any time a transaction is made to be scheduled on the signal. Here the process drives the entity output port.

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