6. (30) Consider a 64B direct-mapped cache with 16B blocks and 4
sets for an 8-bit architecture (i.e., 256 bytes of memory):
a. (5) Write a C function unsigned char getTag(unsigned char
address) that returns the cache tag for the specified address using
bitwise operators:
b. (5) Write a C function unsigned char getSet(unsigned char address) that returns the cache set for the specified address using bitwise operators:
c. (10) Considering the following sequence of memory addresses, which addresses will result in cache hits and which will result in misses (assuming that the cache is initially empty)? For each address, show the tag, set, offset, and whether it resulted in hit or miss:
0x00 0x46 0x06 0x40 0x12 0x0c
d. (10) Now assume that cache is 2-way set associative with 2 sets rather than direct mapped with 4 sets, but that the parameters are otherwise unchaged. Use the Least Recently Used (LRU) eviction policy if evictions are necessary. Again consider the following sequence of memory addresses; for each address, show the tag, set, offset, and whether it resulted in hit or miss:
0x00 0x46 0x06 0x40 0x12 0x0c
(a)C program
#include<stdio.h>
//least 3 bit is offset (block size = 8byte offset = 3
bit)
unsigned char getOffset(unsigned char address){
return address&0x07;
}
//next 2 bit left to offset is set bit(set = (cache size)/block
size 32/8 = 4 (2 bit))
unsigned char getSet(unsigned char address){
return (address>>3)&(0x03);
}
int main(){
unsigned char ch = 'M';
printf("Offset : %d\n",getOffset(ch));
printf("Set : %d",getSet(ch));
return 0;
}
//sample output
(C)(D)
6. (30) Consider a 64B direct-mapped cache with 16B blocks and 4 sets for an 8-bit architecture (...
Module 10 Assignment - Direct-mapped Cache Direct-Mapped Cache In this question you're given a 16-byte memory segment and an 8-byte cache. Given the following series of memory accesses, complete the table below. Use the first Contents/Tag column to insert an item to the cache the first time and use the second Contents/Tag column if a cache entry is overwritten. Note: no index will have more than two blocks mapped to it. The first two examples have been provided. How many...
Question 33 10 pts For a direct mapped cache of 4 blocks with a cache block size of 1 byte, in which cache block will each memory location map to? The order of accesses if given by the operation number. Indicate if each access is a hit or a miss, and what the tag value is for each entry. Assume that the cache is initially empty, and the accesses are in order of appearance. REDRAW AND COMPLETE THE CACHE TABLE...
We have a 4 KB direct-mapped data cache with 4-byte blocks. Consider this address trace: 0x48014554 0x48014548 0x48014754 0x48034760 0x48014554 0x48014560 0x48014760 0x48014554 For this cache, for each address in the above trace, show the tag, index and offset in binary (or hex). Indicate whether each reference is a hit or a miss. What is the miss rate?
6. a) Consider a direct mapped cache with 10 blocks of 10 words each. Suppose main memory is 1000 words. For each memory address below say what cache block it maps to, what is the offset, and what is the tag. 934, 666, 348, 522
a) Suppose we have a 64 KB, direct-mapped cache with 8-word blocks. Determine how many bits are required for the tag, index, and offset fields for a 32-bit memory address. b) If instead, we use a 64 KB, 4-way set-associative cache with 8-word blocks, how many bits will be required for the tag, index, and offset fields for a 32-bit address? c) What type of cache is shown in problem 2? How many bits are required for this cache’s tag,...
Consider a direct-mapped cache with 32 blocks Cache is initially empty, Block size = 16 bytes The following memory addresses (in hexadecimal) are referenced: 0x2B4, 0x2B8, 0x2BC, 0x3E8, 0x3EC,0x4F0, 0x8F4, 0x8F8, 0x8FC. Map addresses to cache blocks and indicate whether hit or miss
Assume the following about a computer with a cache: .. The memory is byte addressable. • Memory accesses are to 1-byte words (not to 4-byte words). .. Addresses are 8 bits wide. .. The cache is 2-way associative cache (E=2), with a 2-byte block size (B=2) and 4 sets (5=4). • The cache contents are as shown below (V="Valid"): Set #Way #0 Way #1 V=1;Tag=0x12; Data = v=1;Tag=0x10; Data = Ox39 0x00 0x26 Ox63 V=1;Tag=0x09; Data = v=1;Tag=0x11; Data =...
Assuming a direct-mapped cache with 4 four-word blocks that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache. The following is a sequence of address references given as word addresses. 1, 5, 8, 4, 17, 19, 20, 6, 9, 8, 43, 5, 6, 21, 9, 17 Reference Hit or Miss Miss 17 19 20 43 Wordo Wordi Word2 Word 3 Block
Targeted Course Learning Outcomes: CLO 2.1 Question 1: Using the “Direct Mapped Cache”, assume that 4-blocks, 1 word/block, direct mapped Initial state is empty as shown below. Index V Tag Data 00 N 01 N 10 N 11 N And the following addresses have been requested in the following sequences: Request 1: Word Addresses 4, 5 and 7 Request 2: Word Addresses 0, 1 and 3 Request 3: Word Addresses 1, 2 and 3 Request 4: Word Addresses 3, 4...
Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...