Question

I need answer for qustion (2)

1. One of the reasons why the MARE architecture is very inefficient is because it only has 1AC Assuming that you have access to many other ACs (AC, AC1, AC2, etc) Assume that in the new MARIE Architecture, you can do ADD 105 AC1 This means: Value @ x105 ACAC or suB 104 AC2 → This means: Valus @ x 104 + AC → AC2 How would your program (Lab #s, Question 1, also page 258) look? 2. Using all the MARIE assembly programs you have written for the previous lab question 2 explain whether adding the following features to MARIE ISA * will speed up or slow down your assembly program. Explain why? (You do not need to weite any assembly programs here) e will complicate or simplify the decoding logic. (You do not need to design any circuiltshere Note: Let's assume that all MARE instructions go through fetch/decode/execute in 3 clock cycles a. MARIE instruction accepts more than 1 operand b. Break up memory into instruction memory and data memory c. Include more operations such as SHIFT, MULT and DIV operations 3. The architecture above is the MIPS architecture. Each instruction is executed in 5 clock cycles a. Is it true that all MIPS programs are slower than MARIE programs. Why or why not? b. Using the instruction ADD R1 R2 R3, explain o what values these instruction signal would have

Answer 1

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