Ques 1.
Initially,
R1 = 0000
R2 = 0072
R3 = 0016
R5 = 4972
AR = 0015
Memory Address |
Content |
0001 |
ABCD |
0002 |
7483 |
……… |
……… |
……… |
……… |
0015 |
A235 |
0016 |
5978 |
a). R2 <- M[AR]
This instruction means that the value stored at the memory location whose address is present in the register AR is copied to the register R2.
We know that AR = 0015
This means that the value stored at the memory location having address 0015 will be copied to R2.
From the current memory snapshot, we can see that the value stored at memory location 0015 = A235
Thus, now R2 = A235
So, the new register values will be:
R1 = 0000
R2 = A235
R3 = 0016
R5 = 4972
AR = 0015
The memory table will remain the same as nothing is being changed in the memory.
b). M[AR] <- R3
This means that the value in register R3 is copied to the memory location whose address is stored in the register AR.
Currently, R3 = 0016 and AR = 0015
Thus, 0016 will be copied to memory location 0015.
This time, the values in the registers will be unchanged, as only the memory is altered.
The new memory table will be:
Memory Address |
Content |
0001 |
ABCD |
0002 |
7483 |
……… |
……… |
……… |
……… |
0015 |
0016 |
0016 |
5978 |
c). R5 <- M[R3]
This instruction is similar to the one in part a).
It means that the value stored at the memory location whose address is present in the register R3 is copied to the register R5.
Currently, R3 = 0016
This means that the value stored at the memory location having address 0016 will be copied to R5.
From the current memory snapshot, we can see that the value stored at memory location 0016 = 5978
Thus, now R5 = 5978
So, the new register values will be:
R1 = 0000
R2 = A235
R3 = 0016
R5 = 4972
AR = 5978
The memory table will remain the same as nothing is being changed in the memory.
Thus, the final values of R1, R2, R3, R5, and AR after the execution of all the instructions are:
R1 = 0000
R2 = A235
R3 = 0016
R5 = 4972
AR = 5978
Ques 2.
There are 32 registers, each of 64 bits.
This means that there must be 64 multiplexers, each of size 32:1.
This is because each of the 64 bits of one register will go as input to the different multiplexers. Thus, we need 64 multiplexers for 64 bits. Now, there are 32 registers. This means that one multiplexer will have 32 inputs (each of the 32 registers having one of their bits as input to the multiplexer).
Now for a multiplexer of size n:1, the number of select inputs for that multiplexer = log2(n)
Thus, in this case, since the size of the multiplexer is 32:1, the number of select inputs = log2(32) = 5
Since 25 = 32, there will be a total of 32 different combinations, each combination will select one of the 32 registers.
Thus the answers to the questions are:
a). The number of selection inputs in each multiplexer = 5
b). Size of each multiplexer = 32:1
c). The number of multiplexers required in the bus = 64
That's it. Hope it helped. I've tried to explain in the simplest way possible. If you have any queries or doubts, please feel free to ask in the comments section. If it helped in any way, please consider giving positive ratings.
CS 304- Quiz 3 (Chapter 4) Time: 45 Minutes (Closed book & notes) Answer all questions clearly Na...