Question

Here is a series of address references given as word addresses: 1, 4, 8, 5, 20, 17, 19, 56, 9, 11...

Here is a series of address references given as word addresses: 1, 4,
8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17.  For each of the following
cache design, label each reference as a hit or a miss and show the final
contents of the cache.  Assume the caches are initially empty.
- Direct mapped with four-word blocks and total size of 16 words.
1 1
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Answer #1

Address reference

Binary address

Hit/Miss

Assigned cache block

1

0001

Miss

0001

4

0100

Miss

0100

8

1000

Miss

1000

5

0101

Miss

0101

20

10100

Miss

0100

17

10001

Miss

0001

19

10011

Miss

0011

56

111000

Miss

1000

9

1001

Miss

1001

11

1011

Miss

1011

4

0100

Miss

0100

43

101011

Miss

1011

5

0101

Hit

0101

6

0110

Miss

0110

9

1001

Hit

1001

17

10001

Hit

0001

Final Contents of Cache after references

Index

0000

0001

0010

0011

0100

0101

0110

0111

Contents

M(17)

M(19)

M(4)

M(5)

M(6)

Index

1000

1001

1010

1011

1100

1101

1110

1111

Contents

M(56)

M(9)

M(43)

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