Question

Verilog code help

Counter is a sequential circuit. A digital circuit which is used for a counting events (usually clock pulses) is known counter. Counter is most clear application of the usage of flip-flops. It is a group of flip-flops with a clock signal applied. Consider the following 4 bits up counter 1. Write mixed behavioral/ structural Verilog code for this counter (HA and Counter structural, D FF behavioral) 2. Write Verilog test bench for this this counter then run the behavioral simulator 3. Bounce question: Modify your counter to act as down counter En Cout A Cout A Carry2 Cout A Carry1 Cout A Carryo НА HA HA НА Sum2 Sum1 Sum3 Sumo Reset Rst Rst D 9 CIk Rst D 9 Clk Rst Clk Clk Count3 Countl Counto

Answer 1

Answer 1)

VERILOG CODE FOR Half Adder, DFF, and Counter

module halfadder(
input A, B,
output S, Cout
);

assign S = A ^ B;
assign Cout = (A & B);

endmodule

module DFF (
input Clk,
input Rst,
input D,
output reg Q
);

always @ (posedge Clk or posedge Rst)
begin
if (Rst)
Q <= 1'd0;
else
Q <= D;
end

endmodule

module counter1 (
input Clk,
input Reset,
input En,
output [3:0] Count
);

wire [3:0] Carry, Sum;

halfadder HA0 (.A(Count[0]), .B(En), .S(Sum[0]), .Cout(Carry[0]));
halfadder HA1 (.A(Count[1]), .B(Carry[0]), .S(Sum[1]), .Cout(Carry[1]));
halfadder HA2 (.A(Count[2]), .B(Carry[1]), .S(Sum[2]), .Cout(Carry[2]));
halfadder HA3 (.A(Count[3]), .B(Carry[2]), .S(Sum[3]), .Cout(Carry[3]));

DFF DFF0 (.Clk(Clk), .Rst(Reset), .D(Sum[0]), .Q(Count[0]));
DFF DFF1 (.Clk(Clk), .Rst(Reset), .D(Sum[1]), .Q(Count[1]));
DFF DFF2 (.Clk(Clk), .Rst(Reset), .D(Sum[2]), .Q(Count[2]));
DFF DFF3 (.Clk(Clk), .Rst(Reset), .D(Sum[3]), .Q(Count[3]));

endmodule

TESTBENCH For UP Counter1

module testbench;
reg Clk;
reg Reset;
reg En;
wire [3:0] Count;

counter1 DUT (.Clk(Clk), .Reset(Reset), .En(En), .Count(Count));

always
#5 Clk = !Clk;

always @(posedge Clk)
$display("Clk = %b, Reset = %d, En = %b, Count = %d", Clk, Reset, En, Count);

initial
begin
Clk = 1'b0;
Reset = 1'b1;
En = 1'b0;
#20;
Reset = 1'b0;
En = 1'b1;
#100;
En = 1'b0;
#60;
En = 1'b1;
#100;
$finish;
end

initial
begin
$recordfile("file1.trn");
$recordvars();
end

endmodule

/*************** Output Of Program *******************
Clk = 1, Reset = 1, En = 0, Count = 0
Clk = 1, Reset = 1, En = 0, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 1
Clk = 1, Reset = 0, En = 1, Count = 2
Clk = 1, Reset = 0, En = 1, Count = 3
Clk = 1, Reset = 0, En = 1, Count = 4
Clk = 1, Reset = 0, En = 1, Count = 5
Clk = 1, Reset = 0, En = 1, Count = 6
Clk = 1, Reset = 0, En = 1, Count = 7
Clk = 1, Reset = 0, En = 1, Count = 8
Clk = 1, Reset = 0, En = 1, Count = 9
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 0, Count = 10
Clk = 1, Reset = 0, En = 1, Count = 10
Clk = 1, Reset = 0, En = 1, Count = 11
Clk = 1, Reset = 0, En = 1, Count = 12
Clk = 1, Reset = 0, En = 1, Count = 13
Clk = 1, Reset = 0, En = 1, Count = 14
Clk = 1, Reset = 0, En = 1, Count = 15
Clk = 1, Reset = 0, En = 1, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 1
Clk = 1, Reset = 0, En = 1, Count = 2
Clk = 1, Reset = 0, En = 1, Count = 3
*************************************************/

Answer 3)

VERILOG Code for Half subtractor, DFF, Down Counter 2

module halfsubtractor(
input A, B,
output S, Cout
);

assign S = A ^ B;
assign Cout = (!A & B);

endmodule

module DFF (
input Clk,
input Rst,
input D,
output reg Q
);

always @ (posedge Clk or posedge Rst)
begin
if (Rst)
Q <= 1'd0;
else
Q <= D;
end

endmodule

module counter2 (
input Clk,
input Reset,
input En,
output [3:0] Count
);

wire [3:0] Carry, Diff;

halfsubtractor HS0 (.A(Count[0]), .B(En), .S(Diff[0]), .Cout(Carry[0]));
halfsubtractor HS1 (.A(Count[1]), .B(Carry[0]), .S(Diff[1]), .Cout(Carry[1]));
halfsubtractor HS2 (.A(Count[2]), .B(Carry[1]), .S(Diff[2]), .Cout(Carry[2]));
halfsubtractor HS3 (.A(Count[3]), .B(Carry[2]), .S(Diff[3]), .Cout(Carry[3]));

DFF DFF0 (.Clk(Clk), .Rst(Reset), .D(Diff[0]), .Q(Count[0]));
DFF DFF1 (.Clk(Clk), .Rst(Reset), .D(Diff[1]), .Q(Count[1]));
DFF DFF2 (.Clk(Clk), .Rst(Reset), .D(Diff[2]), .Q(Count[2]));
DFF DFF3 (.Clk(Clk), .Rst(Reset), .D(Diff[3]), .Q(Count[3]));

endmodule

TESTBENCH FOR DOWN COUNTER2

module testbench;
reg Clk;
reg Reset;
reg En;
wire [3:0] Count;

counter2 DUT (.Clk(Clk), .Reset(Reset), .En(En), .Count(Count));

always
#5 Clk = !Clk;

always @(posedge Clk)
$display("Clk = %b, Reset = %d, En = %b, Count = %d", Clk, Reset, En, Count);

initial
begin
Clk = 1'b0;
Reset = 1'b1;
En = 1'b0;
#20;
Reset = 1'b0;
En = 1'b1;
#100;
En = 1'b0;
#60;
En = 1'b1;
#100;
$finish;
end

initial
begin
$recordfile("file1.trn");
$recordvars();
end

endmodule

/*************** Output Of Program *******************
Clk = 1, Reset = 1, En = 0, Count = 0
Clk = 1, Reset = 1, En = 0, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 15
Clk = 1, Reset = 0, En = 1, Count = 14
Clk = 1, Reset = 0, En = 1, Count = 13
Clk = 1, Reset = 0, En = 1, Count = 12
Clk = 1, Reset = 0, En = 1, Count = 11
Clk = 1, Reset = 0, En = 1, Count = 10
Clk = 1, Reset = 0, En = 1, Count = 9
Clk = 1, Reset = 0, En = 1, Count = 8
Clk = 1, Reset = 0, En = 1, Count = 7
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 0, Count = 6
Clk = 1, Reset = 0, En = 1, Count = 6
Clk = 1, Reset = 0, En = 1, Count = 5
Clk = 1, Reset = 0, En = 1, Count = 4
Clk = 1, Reset = 0, En = 1, Count = 3
Clk = 1, Reset = 0, En = 1, Count = 2
Clk = 1, Reset = 0, En = 1, Count = 1
Clk = 1, Reset = 0, En = 1, Count = 0
Clk = 1, Reset = 0, En = 1, Count = 15
Clk = 1, Reset = 0, En = 1, Count = 14
Clk = 1, Reset = 0, En = 1, Count = 13
*****************************************************/