The logic behind the below code is that the circuit accepts the binary value of month and leap year as inputs and outputs the number of days in the month.
If the input month is of numbers 4,6,9,11(April,June,September,November) result of number of days is 30
If the input month is 2 (Feb) and input leap year is 0 number of days is displayed as 28
If the input month is 2(Feb) and input leap year is 1,number of days is 29.
If none of the above condition is true then the number of days is considered as 31.
Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Number_Of_Days_In_Month is
port (
Month : in unsigned(3 downto 0);
LeapYear : in std_logic;
NumberOfDays: out unsigned(4 downto 0)
);
end entity Number_Of_Days_In_Month;
architecture Number_Of_Days_In_Month_combinational of Number_Of_Days_In_Month is
signal days_28 : std_logic;
signal days_29 : std_logic;
signal days_30 : std_logic;
signal days_31 : std_logic;
begin
days_30 <= '1' when Month= 9 or
Month= 4 or
Month = 6 or
Month = 11
else '0';
days_28 <= '1' when Month= 2 and
LeapYear = '0'
else '0';
days_29 <= '1' when Month = 2 and
LeapYear = '1'
else '0';
days_31 <= '1' when days_30 = '0' and
days_28 = '0' and
days_29 = '0'
else '0';
NumberOfDays <= to_unsigned(30,NumberOfDays'length) when days_30d = '1' else
to_unsigned(28,NumberOfDays'length) when days_28d = '1' else
to_unsigned(29,NumberOfDays'length) when days_29d = '1' else
to_unsigned(31,NumberOfDays'length) when days_31d = '1' else
to_unsigned(0,NumberOfDays'length);
end architecture Number_Of_Days_In_Month_combinational;
Write a VHDL module that implements a combinational dircuit that indicates the number of days in a given month. Notes: Q4) .. The month input is a single port (4-bit number The Leap Year port indicat...
Q4) Write a VHDL module that implements a combinational circuit that indicates the number of days in a given month. Notes: The month input is a single port (4-bit number). 'The Leap_Year port indicate if it is a leap year. The outputs must be 4 separate ports. Invalid months should result in no outputs active. Q4) Write a VHDL module that implements a combinational circuit that indicates the number of days in a given month. Notes: The month input is...