Question

Design a sequential system that has one synchronous input bit stream x and one output z, with the following functionality and also follows the design constrains.

Design Specifications: Design a sequential system that has one synchronous input bit stream X and one output Z, with the following functionality 1) We look at every fourth-input-bit, while the other input bits are "don't cares". when three "consecutives" fourth-bits form the sequences 110 or 000 the system should output Z = 1, meaning it detected the desired sequences of fourth-bits, otherwise the output is Z 0 The detection should occur, at your discretion, when the event occurs with the arrival of each fourth-bit or one clock cycle after the event occurs The detection is with "overlap" when possible, meaning that the previous one or two fourth-bits can be reused if they help to conform the required input sequence The timing trace below (Mealy-type) depict a possible example with three events in order to clarify the prescribed functionality Discuss any timing problem that you think your design solution may have, and give a possible alternative 2) 3) 4) 5) 6) X 1O11 0O 0 1 0 1 011 100O 01 1 101 0 100 1 1001 Z 00 0 0 0 0 0 0 0 0 SYSTEM Subsystem 1 Subsystem N Design Constraints: 1. Do not use more than 4 Flip-Flops of any type 2. Do not use more than 5 discrete gates of any type (each with three inputs or less) 3. Do not use decoders or multiplexers 4. The system can use any number of subsystems 5. The detection should occur, at your discretion, when the event occurs with the arrival of each fourth-bit or one clock cycle after the event occurs Note: Every time you cannot meet one of the constraints you may lose some points (for example if you use five, instead of four Flip Flops)

Answer 1

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