Question

For the MOS transistor circuit below, the capacitor is discharged in the beginning.

0.2V, β = 0.2mA/V2, and C = 1mF. VDD-1V, VTH For the clock voltage shown, plot the voltage waveform vc(t) and label its steady state values. CLK м, VDD

Answer 1

Here CLK is applied at gate terminals.

V_D = 1V, V_G=1V > V_TH = 0.2 V i.e V_D > V_G - V_TH . So the MOSFET is ON and in saturation when CLK = 1 and the voltage drop appears across MOSFET and when CLK=0, MOSFET is OFF and V_DD appears across capacitor. So v_c(t) looks like

CLK op >七

Hope you understood.