Question

Daw the loguc Diagram of Darallel outs So Sdhe regster operate cccording to the lolawing table a 2-bt Parallel in ester wit miede selection npuls Register opeatien Ne chae Campleant autputs Clear register ta Lead parallel dae (XzXiX

Answer 1

Solution:

The register is designed using Verilog Hardware description language.

//+++++++++++ Code starts here ++++++++++++//

module PIPO(x,clk,s0,s1,q);
input [2:0] x;
input clk,s0,s1;
output reg [2:0] q;

always @(posedge clk) begin
if(s0==0 && s1==0)
       q<=x;
else if(s0==0 && s1==1)
       q<=~q;
else if(s0==1 && s1==0)
       q<=3'b0;
else
       q<=x;
end
endmodule

//++++++++++++++++ END ++++++++++++++++//

Simulate that code and synthesize it.The corresponding schematic would be created using the view RTL schematic icon(below the synthesize - XST icon).

N.B: Copy the code and save it in a ( .v ) file and simulate using verilog simulator .