Question

****Verilog ***

Why does a non-project mode synthesis provide more comprehensive synthesis/PAR reports versus project mode?

What is Hard IP versus Soft IP

Visual Example

Answer 1

Understanding project mode and non - project mode :

The vivado design suite enables you to run the tools using different methods depending on your preference. You can elect to use a project based method to automatically manage your design process and design data, also known as project mode.

Alternatively, you can choose a Tcl script based compilation style method in which you manage sources and the design process yourself, also known as non project mode.

The following automated features are only avail when using project mode :

1. Source file for management and status

2.Consolidated messages and automatically generated standard reports

3.storage and reuse of tool settings and design configuration

4.use and management of constraint sets

5.flow navigator

6.project summary

In non project mode, each action is executed using a Tcl command. All of the processing is done in memory, so no files or reports are generated automatically. Each time you compile the design, you must define all of the sources, set all tool and design configuration parameters,launch all implementation commands, and generate report files. Because project is not created no disk, source files remain in their original locations and design output is only created when and where you specify. This method provides you with all of the power of Tcl commands and full control over the entire design process.

Non project mode advantages

1.Manage hdl source files, constraints and IP.

2.manage dependencies.

3.Generate and store synthesis and implementation results.

Hard IP versus soft IP

An IP Core in semiconductors is a reusable unit of logic or functionality or a cell or a layout design that is normally developed with the idea of licensing to multiple vendor for using as building blocks in different chip designs.

Soft IP cores are IP blocks generally offered as synthesizable RTL models. These are developed in one system verilog or VHDL

Sometimes IP cores are also synthesized and provided as generic gate level netlist which can be then mapped to any process technologies. This also falls under soft IP cores. The advantage of soft IP cores is that those routing flow by a consumer to map to any process technologies.

Example: DRAM controller IP, Ethernet MAC IP, AMBA bus protocol IP etc..

Hard IP cores on the other hand are offered as layout designs in a layout format like GDS which is mapped to a process technology and can be directly dropped by a consumer to the final layout of the chip. These cores cannot be customised for different process technologies.

Example : Analog and mixed signal logic designs for series, PLL, ADC, DAC, phy layer logic for DDC etc