Question

A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA : 800 ps A. What is the frequency of this machine without a pipeline? B.What is the frequency for a pipelined version of this CPU? C. What is the datapath for the pipeline - that is, what functional units Cache 2 Base machine has a 2.4GHZ clock rate. There is L1 and L2 cache L1 cache is 256K, direct mapped write through. 90% (read) hit rate. All writes take 1 cycle, reads take one cycle in cache, 4 cycles for miss. L2 cache is 2MB, 4 way set associative write back. 99.5% hit rate, 60 cycle miss penalty (writes handled by cache hardware so no penalty).

Answer 1

Answer:

In case of Pipelined approach, maximum amount of time consumed by CPU for each unit of task is 240ps.So considering that all task are completed in 1 clock cycle only, each clock cycle cannot be less than 240ps (so taht we can accomodate all cases). So if the time period is at least 240ps,so cpu frequency would be at most 4.16Mhz In the other case where no pipelines are being used, each instruction will be executed without parrallism. So looking into the table, we can say that without the use of pipeline, the clock period should be atleast be 800ms, so the clock frequency can be atmost be 1.25MHZ Basic five-stage pipeline are IF = Instruction Fetch, ID Instruction Decode, EX Execute, MEM = Memory access, and WBd Register write back. CamScanner

1 ) Given that L1 cache has hit rate 90 % then miss rate in L1 10% L2 cache has hit rate 99.5% then miss rate in L2 0.5% Cache L1 miss penalty 4 clock cycles Cache L2 miss penalty 60 clock cycles (L2 access time) 64 cycles Memory access time 4+ 60 formula for CPI 1 % instructions that miss in L1 x (L2access-time instructions that miss in L2 x Memory access-time) CPI 110% x (60 0.5 %x 64) 1 0.1 x (60 +0.32) 1+ 0.1 x (60.32) 1 6.032 CPI 7.032 cycles per instruction for read write operations Given that write and read instructions 40% frequency with CPI 7.032 Remaining 60 % percent instructions takes 1 clock cycle There fore CPI for all instructions7.0321 8.032 2) Given that L1 cache changed hit rate 95% Initial clock rate 2.4 Ghz now clock rate= 2.2 Ghz remaining al1 are same as 1st problem. CPI 1% instructions that miss in L1 x (L2access-time instructions that miss in L2 x Memory access-time) CPI 1 5% x (600.5 %x 64) 1+ 0.05 x (60 +0.32) 1+ 0.05 x (60.32) 1+ 3.016 CPI 4.016 cycles per instruction for read/write operations ->Given that write and read instructions 40% frequency with CPI 4.016 akes 1 clock cycle ->Remaining 60 % percent instructions 4.016 1 5.016 There fore CPI for all instructions performance ratio (8.032 5.016) x (2.2/2.4) =1.601 x 0.916 1.467 1+ 0.467 i.e 46.7 % improvement after modifying L1 cache hit ratioa and clock rate. Scanned with This a 46.7% improvement, which is probably worth the effort. CamScanner