6. In each of the instructions shown below, assume that the label LOOP corresponds to memory...
6. In each of the instructions shown below, assume that the label LOOP corresponds to memory address 0x40CE0078.
a) (5) Show in hex the 32-bit machine code for the instruction bltzal $14,LOOP
Assume that the machine code will be located at address 0x40CE8880.
b) (5) Register $14 contains negative 2 in two’s complement form. Show, in hex (0xdddddddd), the 32-bit contents of all registers within the CPU that are modified when the instruction bltzal $14,LOOP is executed..
c) 5) Show in hex (0xdddddddd) the 32-bit machine code for the instruction j LOOP.
Assume that the machine code will be located at address 0x40CE88C0.
d) (5) Show in hex (0xdddddddd) the 32-bit contents of all registers within the CPU that are modified as a result of executing the instruction j LOOP.
Homework Answers
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6. In each of the instructions shown below, assume that the label LOOP corresponds to memory...
The registers in the HCS12 show the following -$2245 x-$1234 Y 5678, SP S0900 Assume the...
The registers in the HCS12 show the following -$2245 x-$1234 Y 5678, SP S0900 Assume the following sequence of code is executed and then specify what is in the stack and what is in the registers psha pshx psha puly What are the register contents after the program sequence is executed: A SP B. Show the contents of the stack after the program sequence is executed (in hexadecimal): Memory Address Memory Contents (hex) Pane 12 of 12
The registers in...
High-level computer languages are created to be understood by humans. As a result, the keywords and...
High-level computer languages are created to be understood by
humans. As a result, the keywords and the commands of these
languages are easy to understand. Machine languages are harder to
understand and operate.
For this assignment, you should assume that the memory cells at
addresses F0 to F9 are in the machine described in FIGURE
1, and that it contains the hexadecimal bit patterns
described in the following table.
Note: Each memory address contains 2 values
that must be used...
Translate each of the following pseudo-instructions into MIPS instructions. You should Produce a minimal sequence of...
Translate each of the following pseudo-instructions into MIPS instructions. You should Produce a minimal sequence of MIPS instructions to accomplish the required computation. (8 Points) 1) bgt $t1, 100, Label # bgt means branch if greater than 2) ble $s2, 10, Next # ble means branch if less than or equal 3) ror $s0, $s4, 7 # ror means rotate right $s4 by 7 bits and store the result in $s0 4) neg $s5, $s4 # $s5 will have the...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which ar...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
can you show me how you get each one or fill the table? Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP regis...
can you show me how you get each one or fill the table?
Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP registers in Table 1 as the program is executed Show new values of memory content in Table 2 if the memory location content is affected. - NOTE: This is a continues program where instruction results affect the instruction that follows Leave...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
6. Write the MIPS assembly code that corresponds to the pseudo code below. Assume that the...
6. Write the MIPS assembly code that corresponds to the pseudo code below. Assume that the address for integer i is baseaddress+4 and the address for a[0] is baseaddress+8. Assume that the baseaddress is stored in $gp. The code initializes i to O; it then iterates from i-0 to i-9, setting a4i in each iteration. To make your code efficient, i must be loaded into a register at the start, and it must be updated in memory only after you've...
Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64...
Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. What's the size of the largest memory space that can be addressed by this computer?Assume byte addressable memory.
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit...
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory. 2. List the operation modes of the ARM Cortex-M3. 3. What is the function of register R13? Register R14? Register R15? 4. On an ARM Cortex-M3, in any given mode, how many registers does a programmer see at one time? 5. Which bits of the ARM Cortex-M3 status registers...
Assume that ‘slt $1, $2, $3’ is executed with the implementation in the picture. Identify the value of the 9-bit control...
Assume that ‘slt $1, $2, $3’ is executed with the implementation
in the picture. Identify the value of the 9-bit control
signals.
Add u X ALU result 4 Add Shift left 2 RegDst Branch MemRead MemtoReg Control ALUOP Instruction [31-26 MemWrite ALUSRC RegWrite Instruction [25-21] Read register 1 Read Read PC address Instruction [20-16] data 1 Read Zero register 2 Instruction ALU ALU 31-0] Instruction memory Read data M Read Address Write result u M Instruction [15-11] register data 2...
The registers in the HCS12 show the following -$2245 x-$1234 Y 5678, SP S0900 Assume the following sequence of code is executed and then specify what is in the stack and what is in the registers psha pshx psha puly What are the register contents after the program sequence is executed: A SP B. Show the contents of the stack after the program sequence is executed (in hexadecimal): Memory Address Memory Contents (hex) Pane 12 of 12
The registers in...
High-level computer languages are created to be understood by
humans. As a result, the keywords and the commands of these
languages are easy to understand. Machine languages are harder to
understand and operate.
For this assignment, you should assume that the memory cells at
addresses F0 to F9 are in the machine described in FIGURE
1, and that it contains the hexadecimal bit patterns
described in the following table.
Note: Each memory address contains 2 values
that must be used...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
can you show me how you get each one or fill the table?
Given the following memory and register values as shown in Tables 1& 2 below: Determine the values of the A, B, X, Y, CCR & SP registers in Table 1 as the program is executed Show new values of memory content in Table 2 if the memory location content is affected. - NOTE: This is a continues program where instruction results affect the instruction that follows Leave...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
6. Write the MIPS assembly code that corresponds to the pseudo code below. Assume that the address for integer i is baseaddress+4 and the address for a[0] is baseaddress+8. Assume that the baseaddress is stored in $gp. The code initializes i to O; it then iterates from i-0 to i-9, setting a4i in each iteration. To make your code efficient, i must be loaded into a register at the start, and it must be updated in memory only after you've...
Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. What's the size of the largest memory space that can be addressed by this computer?Assume byte addressable memory.
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory. 2. List the operation modes of the ARM Cortex-M3. 3. What is the function of register R13? Register R14? Register R15? 4. On an ARM Cortex-M3, in any given mode, how many registers does a programmer see at one time? 5. Which bits of the ARM Cortex-M3 status registers...
Assume that ‘slt $1, $2, $3’ is executed with the implementation
in the picture. Identify the value of the 9-bit control
signals.
Add u X ALU result 4 Add Shift left 2 RegDst Branch MemRead MemtoReg Control ALUOP Instruction [31-26 MemWrite ALUSRC RegWrite Instruction [25-21] Read register 1 Read Read PC address Instruction [20-16] data 1 Read Zero register 2 Instruction ALU ALU 31-0] Instruction memory Read data M Read Address Write result u M Instruction [15-11] register data 2...
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