Question

The following register transfers are to be executed in, with minimum clock cycles:
S1' * S0' : R3 <- R0, R1 <- R2

S1 * S0': R2 <- R0, R1 <- R3

S1' * S0 : R3 <- R1, R0 <- R2

S1 * S0 : R2 <- R1, R0 <- R3

(a)What is the minimum number of buses required? Construct the register transfer operations so that the transfers can occur in one clock indicate the individual load line for each of the registers.

(b)Draw a block diagram connecting registers and multiplexers to implement the transfers

Answer 1

Solution:

The selection lines S1 and S0 indicate the registers to be selected. Usually, a bus system will multiplex k reg of n bits to produce n line common bus. Hence 4 common bus line will be chosen.

Register A-> S0' and S1'

Register B-> S0' and S1

Register C-> S0 and S1'

Register D-> S0 and S1

4 x1 4x 1 4 x 4x 1 MUX3 MUX 2 MUX I MUX0 3 2 0 2 0 3 2 0 3 2 0 D. C. B D. C D, с, R B. B 3 210 |3 2 0 3 2 0 3210 Register D Register B Register C Register A

The graphical diagram of three state buffer is

Normal input A if Ca0 Control inpur C