The exclusive-OR circuit of Fig. 3.30 (a) has gates with a delay of 3 ns for an inverter, a 6 ns delay for an AND gate, and a 8 ns delay for an OR gate. The input of the circuit goes from xy = 00 to xy = 01.
(a) Determine the signals at the output of each gate from t = 0 to t = 50 ns.
(b) Write a Verilog gate-level description of the circuit, including the delays.
(c) Write a stimulus module (i.e., a test bench similar to HDL Example 3.3 ), and simulate the circuit to verify the answer in part (a).
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