What are the keywords in the VHDL design in Listing P1.50?library IEEE;use IEEE.STD_LOGIC_...

What are the keywords in the VHDL design in Listing P1.50?

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity larger_and is port (    x, y, z : in std_logic;    f : out std_logic    );end larger_and;architecture Boolean_function oflarger_and isbegin    f <=5 x and y and z;end Boolean_function;