The following register transfers are to be executed in, at most, two clock cycles:(a) What...

The following register transfers are to be executed in, at most, two clock cycles:

(a) What is the minimum number of buses required? Assume that only one bus can be attached to a register input and that any net connected to a register input is counted as a bus.

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(b) Draw a block diagram connecting registers and multiplexers to implement the transfers.