13.5 The bonding pads in I/O circuits are implemented in topmost metal layer with a dimension of 75μm x 75μm. If the separation of the topmost metal layer with SiO2 from the common substrate layer (ground plane) is 1μm,
(a) What is the parasitic capacitance of the bonding pad?
(b) What is the total parasitic capacitance of the bonding pad node if it is connected to a CMOS inverter gate (Wp= 10 μm, Wn =5 μm,LM= 1 μm,tox=500 Å)and also to the output of a tristatable buffer (Wp= 1000 μm, Wn= 500 μm, LM= 1 μm).
The other dimension of the drains is 3μm and the parasitic capacitance in the drain is Cjo=0.3 fF/μm2, Cjsw = 0.5 fF/μm.
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