Solutions For Digital Design Chapter 3 Problem 38P

Write the Verilog gate-level implementation of the circuit.

primitive UDP_02467(D,A,B,C);

output D;

input A,B,C;

table

// A B C D //

0 0 0 : 1;

0 0 1 : 0;

0 1 0 : 1;

0 1 1 : 0;

1 0 0 : 1;

1 0 1 : 0;

1 1 0 : 1;

1 1 1 : 1;

endtable

endprimitive

From the information provided, declare a Verilog module to represent the full circuit. The circuit is to have two external outputs, E and F, and four external inputs, A, B, C, and D. The outputs and inputs are wired correctly by instantiating one instance of UDP_02467 and one additional AND gate.

Write the resultant Verilog code for the circuit.

module Circuit_with_UDP_02467(E,F,A,B,C,D);

output E,F;

input A,B,C,D;

UDP_02467(E,A,B,C);

and(F,E,D);

endmodule

Write the Verilog test bench which will be used to simulate the circuit. All inputs are declared using the reg keyword and all outputs are declared using the wire keyword. The system module is then instantiated with the corresponding inputs and outputs. An initial statement is used to create an input sequence by toggling the inputs, A, B, C, and D every 10 time units or so. The final initial statement is used to terminate runtime at 100 time units.

Write the resultant Verilog test bench to simulate the module.

module t_Circuit_with_UDP_02467;

wire E,F;

reg A,B,C,D;

Circuit_with_UDP_02467 M1(E,F,A,B,C,D);

initial begin

A=1'b1; B=1'b1; C=1'b0; D=1'b0;

#10 A=1'b1; B=1'b1; C=1'b1; D=1'b0;

#5 A=1'b1; B=1'b1; C=1'b1; D=1'b1;

#5 A=1'b1; B=1'b0; C=1'b0; D=1'b1;

#10 A=1'b1; B=1'b0; C=1'b1; D=1'b0;

#10 A=1'b0; B=1'b1; C=1'b0; D=1'b0;

#10 A=1'b0; B=1'b1; C=1'b1; D=1'b1;

#10 A=1'b0; B=1'b0; C=1'b0; D=1'b1;

#10 A=1'b0; B=1'b0; C=1'b1; D=1'b0;

end

initial #100 $finish;

endmodule

Figure 2

The waveform in Figure 2 shows the final simulation of test bench. In every case, the simulation shows the correct value of output lines E and F based on the input provided.