Assume that the largest decoder that can be used in an m × 1 RAM chip has 14 address inputs and that coincident decoding is employed. In order to construct RAM chips that contain more one-bit words than m, multiple RAM cell arrays, each with decoders and read/write circuits, are included in the chip.
(a) With the decoder restrictions given, how many RAM cell arrays are required to construct a 2G × 1 RAM chip?
(b) Show the decoder required to select from among the different RAM arrays in the chip and its connections to address bits and cell array select (CS) bits.
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