A logic circuit with active-low synchronous reset has two control inputs x and y. If x is 1 and y is 0, register R is incremented by 1 and control goes to a second state. If x is 0 and y is 1, register R is cleared to zero and control goes from the initial state to a third state. Otherwise, control stays in the initial state. Draw (1) a block diagram showing the controller, datapath unit (with internal registers), and signals, and (2) the portion of an ASMD chart starting from an initial state.
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