Consider the following matrix transpose routine: Assume this code runs...

Consider the following matrix transpose routine:

Assume this code runs on a machine with the following properties:

• . sizeof(int) == 4.

• . The src array starts at address 0 and the dst array starts at address 64 (decimal).

• . There is a single L1 data cache that is direct-mapped, write-through, write -allocate, with a block size of 16 bytes.

• . The cache has a total size of 32 data bytes and the cache is initially empty.

• . Accesses to the src and dst arrays are the only sources of read and write misses, respectively.

A. For each row and col, indicate whether the access to src[row][col] and dst[row][col] is a hit (h) or a miss (m). For example, reading src[0][0] is a miss and writing dst[0][0] is also a miss.