Modify the design of the serial adder shown in Fig. 6.5 by removing the gated clock to t...

Modify the design of the serial adder shown in Fig. 6.5 by removing the gated clock to the D flip-flop and supplying the clock signal to it directly. Augment the D flip-flop with a mux to recirculate the contents of the flip-flop when shifting is suspended and provide the carry out of the full adder when shifting is active. The shift registers are to incorporate this feature also, rather than use a gated clock. The top-level of the design is to instantiate modules using behavioral models for the shift registers, full adder, D flip-flop, and mux. Assume asynchronous reset. Develop a test bench to simulate the circuit and demonstrate the transfer of data.